公开(公告)号：US20210305255A1

公开(公告)日：2021-09-30

申请号：US16828507

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Juan G. ALZATE VINASCO ,  Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Kimberly L. PIERCE ,  Elliot N. TAN ,  Yu-Jin CHEN ,  Van H. LE ,  Pei-Hua WANG ,  Bernhard SELL

IPC: H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02

Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.