公开(公告)号：US20200007329A1

公开(公告)日：2020-01-02

申请号：US16022619

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： James GUILFORD ,  Vinodh GOPAL ,  Kirk YAP

IPC: H04L9/32 ,  H04L9/06

Abstract: Disclosed embodiments relate to encrypting or decrypting confidential data with additional authentication data by an accelerator and a processor. In one example, a processor includes processor circuitry to compute a first hash of a first block of data stored in a memory, store the first hash in the memory, and generate an authentication tag based in part on a second hash. The processor further includes accelerator circuitry to obtain the first hash from the memory, decrypt a second block of data using the first hash, and compute the second hash based in part on the first hash and the second block of data.

公开(公告)号：US20210351790A1

公开(公告)日：2021-11-11

申请号：US16872144

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： James GUILFORD ,  Vinodh GOPAL ,  Dan CUTTER ,  Kirk YAP ,  Wajdi FEGHALI ,  George POWLEY

IPC: H03M7/30 ,  H03M7/46

Abstract: A lossless data compressor of an aspect includes a first lossless data compressor circuitry coupled to receive input data. The first lossless data compressor circuitry is to apply a first lossless data compression approach to compress the input data to generate intermediate compressed data. The apparatus also includes a second lossless data compressor circuitry coupled with the first lossless data compressor circuitry to receive the intermediate compressed data. The second lossless data compressor circuitry is to apply a second lossless data compression approach to compress at least some of the intermediate compressed data to generate compressed data. The second lossless data compression approach different than the first lossless data compression approach. Lossless data decompressors are also disclosed, as are methods of lossless data compression and decompression.

公开(公告)号：US20190310848A1

公开(公告)日：2019-10-10

申请号：US16452390

申请日：2019-06-25

Applicant: INTEL CORPORATION

Inventor： Vinodh GOPAL ,  Wajdi FEGHALI ,  Gilbert WOLRICH ,  Kirk YAP

IPC: G06F9/30

Abstract: An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, in one embodiment, a processor comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.