中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

31 records (took 0.027 seconds)

    METHOD AND APPARATUS FOR DECOMPRESSION HARDWARE COPY ENGINE WITH EFFICIENT SEQUENCE OVERLAPPING COPY
    1.
    发明申请
    METHOD AND APPARATUS FOR DECOMPRESSION HARDWARE COPY ENGINE WITH EFFICIENT SEQUENCE OVERLAPPING COPY 有权

    公开(公告)号：US20250004772A1

    公开(公告)日：2025-01-02

    申请号：US18217499

    申请日：2023-06-30

    Applicant: Intel Corporation

    Inventor： Kamlesh PILLAI ,  Vinodh GOPAL ,  Gurpreet Singh KALSI ,  Sreenivas SUBRAMONEY ,  Wajdi K. FEGHALI

    IPC: G06F9/30

    Abstract: Apparatus and method for a decompression hardware copy engine with efficient sequence overlapping copy. For example, one embodiment of an apparatus comprises: a plurality of processing cores, one or more of the plurality of processing cores to execute program code to produce a plurality of literals and sequences from a compressed data stream; and decompression acceleration circuitry to generate a decompressed data stream based on the plurality of literals and sequences, the decompression acceleration circuitry comprising: a sequence pre-processor circuit to process batches of sequences of the plurality of sequences and generate a plurality of copy instructions, the sequence pre-processor circuit to merge multiple copy operations corresponding to multiple sequences into a merged copy instruction; and a copy engine circuit to execute the copy instructions to produce the decompressed data stream.

    APPARATUS AND METHOD FOR TWO-STAGE LOSSLESS DATA COMPRESSION, AND TWO-STAGE LOSSLESS DATA DECOMPRESSION
    2.
    发明申请
    APPARATUS AND METHOD FOR TWO-STAGE LOSSLESS DATA COMPRESSION, AND TWO-STAGE LOSSLESS DATA DECOMPRESSION 有权

    公开(公告)号：US20210351790A1

    公开(公告)日：2021-11-11

    申请号：US16872144

    申请日：2020-05-11

    Applicant: Intel Corporation

    Inventor： James GUILFORD ,  Vinodh GOPAL ,  Dan CUTTER ,  Kirk YAP ,  Wajdi FEGHALI ,  George POWLEY

    IPC: H03M7/30 ,  H03M7/46

    Abstract: A lossless data compressor of an aspect includes a first lossless data compressor circuitry coupled to receive input data. The first lossless data compressor circuitry is to apply a first lossless data compression approach to compress the input data to generate intermediate compressed data. The apparatus also includes a second lossless data compressor circuitry coupled with the first lossless data compressor circuitry to receive the intermediate compressed data. The second lossless data compressor circuitry is to apply a second lossless data compression approach to compress at least some of the intermediate compressed data to generate compressed data. The second lossless data compression approach different than the first lossless data compression approach. Lossless data decompressors are also disclosed, as are methods of lossless data compression and decompression.

    EDGE COMPUTING OVER DISAGGREGATED RADIO ACCESS NETWORK FUNCTIONS
    5.
    发明申请
    EDGE COMPUTING OVER DISAGGREGATED RADIO ACCESS NETWORK FUNCTIONS 有权

    公开(公告)号：US20220232423A1

    公开(公告)日：2022-07-21

    申请号：US17704658

    申请日：2022-03-25

    Applicant: Intel Corporation

    Inventor： Akhilesh THYAGATURU ,  Mohit GARG ,  Vinodh GOPAL ,  Ned M. SMITH

    IPC: H04W28/18 ,  H04W28/08

    Abstract: The present disclosure describes edge computing over disaggregated radio access network (RAN) infrastructure through dynamic edge data extraction. Edge data is extracted at intermediate stages of RAN processing, provided to edge compute functions, and inserted back into the RAN processing pipeline. These mechanisms allow for the processing of edge data traffic much closer to the data source than existing approaches, which decreases the overall latency and delay. Additionally, these mechanisms do not require changes to already existing network protocols, allowing for non-complex adoption and implementation.

    EFFICIENT ACCELERATOR OFFLOAD IN MULTI-ACCELERATOR FRAMEWORK
    7.
    发明申请
    EFFICIENT ACCELERATOR OFFLOAD IN MULTI-ACCELERATOR FRAMEWORK 有权

    公开(公告)号：US20220075655A1

    公开(公告)日：2022-03-10

    申请号：US17529149

    申请日：2021-11-17

    Applicant: Intel Corporation

    Inventor： Akhilesh S. THYAGATURU ,  Mohit Kumar GARG ,  Vinodh GOPAL

    IPC: G06F9/50

    Abstract: Methods, apparatus, and software for efficient accelerator offload in multi-accelerator frameworks. One multi-accelerator framework employs a compute platform including a plurality of processor cores and a plurality of accelerator devices. An application is executed on a first core and a portion of the application workload is offloaded to a first accelerator device. In connection with moving execution of the application to a second core, a second accelerator devices to be used for the offloaded workload is selected based on core-to-accelerator cost information for the second core. This core-to-accelerator cost information includes core-accelerator cost information for combinations of core-accelerator pairs, which are based, at least on part, on latencies projected for interconnect paths between cores and accelerators. Both single-socket and multi-socket platform are supported. The solutions include mechanisms for moving offloaded workloads for multiple accelerator devices, as well as synchronizing accelerator operations and workflows.

    APPARATUS AND METHOD FOR EXECUTING BOOLEAN FUNCTIONS VIA FORMING INDEXES TO AN IMMEDIATE VALUE FROM SOURCE REGISTER BITS
    9.
    发明申请
    APPARATUS AND METHOD FOR EXECUTING BOOLEAN FUNCTIONS VIA FORMING INDEXES TO AN IMMEDIATE VALUE FROM SOURCE REGISTER BITS 审中-公开

    公开(公告)号：US20190310848A1

    公开(公告)日：2019-10-10

    申请号：US16452390

    申请日：2019-06-25

    Applicant: INTEL CORPORATION

    Inventor： Vinodh GOPAL ,  Wajdi FEGHALI ,  Gilbert WOLRICH ,  Kirk YAP

    IPC: G06F9/30

    Abstract: An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, in one embodiment, a processor comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.

Patent Agency Ranking