公开(公告)号：US20200211952A1

公开(公告)日：2020-07-02

申请号：US16814215

申请日：2020-03-10

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Kousik Ganesan ,  Marcel Arlan Wall ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/10 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.

公开(公告)号：US20200006273A1

公开(公告)日：2020-01-02

申请号：US16022453

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Kousik Ganesan ,  Suddhasattwa Nad ,  Thomas Heaton ,  Sri Chaitra Jyotsna Chavali ,  Amruthavalli Pallavi Alur

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A microelectronic device is formed including two or more structures physically and electrically engaged with one another through coupling of conductive features on the two structures. The conductive features may be configured to be tolerant of bump thickness variation in either of the structures. Such bump thickness variation tolerance can result from a contact structure on a first structure including a protrusion configured to extend in the direction of the second structure and to engage a deformable material on that second structure.

公开(公告)号：US10658281B2

公开(公告)日：2020-05-19

申请号：US15721321

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Kousik Ganesan ,  Marcel Arlan Wall ,  Srinivas Pietambaram

IPC: H05K7/10 ,  H05K7/12 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/10 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.

公开(公告)号：US20190103348A1

公开(公告)日：2019-04-04

申请号：US15721321

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Rahul N. Manepalli ,  Kousik Ganesan ,  Marcel Arlan Wall ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/10 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

Abstract: According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.