公开(公告)号：US20220077856A1

公开(公告)日：2022-03-10

申请号：US17525894

申请日：2021-11-13

Applicant: Intel Corporation

Inventor： Yi Peng ,  Brandon Gordon ,  Mahesh A. Iyer ,  Krishna Nagar

IPC: H03K19/177 ,  G06F30/343

Abstract: An integrated circuit includes a monitored circuit and a signal analyzer circuit. The signal analyzer circuit includes a logic circuit that determines if a condition signal satisfies a condition to generate an output signal. A first-in-first-out (FIFO) buffer circuit stores opportunistic data indicated by a monitored signal received from the monitored circuit in response to the output signal indicating if the condition signal satisfies the condition. A communication channel transmits the opportunistic data stored in the FIFO buffer circuit outside the integrated circuit.

公开(公告)号：US20220075688A1

公开(公告)日：2022-03-10

申请号：US17525917

申请日：2021-11-14

Applicant: Intel Corporation

Inventor： Krishna Nagar ,  Brandon Gordon ,  Yi Peng

IPC: G06F11/10 ,  G06F3/06

Abstract: An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.