公开(公告)号：US20240289168A1

公开(公告)日：2024-08-29

申请号：US18506687

申请日：2023-11-10

Applicant: Intel Corporation

Inventor： Krishnan Ananthanarayanan ,  Martin Langhammer ,  Om Ji Omer ,  Bogdan Pasca ,  Kamlesh Pillai ,  Pramod Udupa

IPC: G06F9/50

CPC classification number: G06F9/5027

Abstract: Systems, apparatuses and methods may provide for technology that identifies a type of a first activation function, identifies a derivative level of the first activation function, and generates a first instruction based on the type of the first activation function and the derivative level of the first activation function. The technology also includes an accelerator having logic coupled to one or more substrates, the logic including a compute engine including a plurality of arithmetic operators, a multiplexer network coupled to the compute engine, and a controller coupled to the multiplexer network, the controller to detect the first instruction, decode the first instruction to identify the first activation function, and drive the multiplexer network to form first connections between two or more of the plurality of arithmetic operators in accordance with the first activation function, wherein the first connections are to cause the compute engine to conduct the first activation function.

公开(公告)号：US20230161626A1

公开(公告)日：2023-05-25

申请号：US18049509

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Gurpreet S. Kalsi ,  Om Ji Omer ,  Prashant Laddha ,  Kamlesh R. Pillai ,  Anirud Thyagharajan ,  Meenal Kudalkar ,  Krishnan Ananthanarayanan ,  Sreenivas Subramoney

IPC: G06F9/50 ,  G06T1/60

CPC classification number: G06F9/5027 ,  G06T1/60

Abstract: An embodiment of an apparatus comprises a hardware accelerator to perform a three-dimensional (3D) point cloud data access operation, and circuitry coupled to the hardware accelerator to control the hardware accelerator to perform the 3D point cloud data access operation in response to a request. Other embodiments are disclosed and claimed.

公开(公告)号：US20230205251A1

公开(公告)日：2023-06-29

申请号：US17562795

申请日：2021-12-27

Applicant: Intel Corporation

Inventor： Santosh Kumar Singh ,  Krishnan Ananthanarayanan

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: Systems or methods of the present disclosure may provide for analyzing or monitoring one or more frequencies of one or more clocks. For example, a clock analysis system includes a control register that stores a frequency indication for a first clock, and an edge counter and a window counter that count respective numbers of edges of the first clock and a second clock within a particular window. The clock analysis system also includes a status register that stores indications of the number of edges from the edge counter and the window counter. The clock analysis system further includes an application processor that determines a ratio between the number of edges of the first clock and the number of edges of the second clock, determines a frequency of the first clock based on the ratio, and transmits an indication of the frequency to a peripheral device for display.