公开(公告)号：US20240289168A1

公开(公告)日：2024-08-29

申请号：US18506687

申请日：2023-11-10

Applicant: Intel Corporation

Inventor： Krishnan Ananthanarayanan ,  Martin Langhammer ,  Om Ji Omer ,  Bogdan Pasca ,  Kamlesh Pillai ,  Pramod Udupa

IPC: G06F9/50

CPC classification number: G06F9/5027

Abstract: Systems, apparatuses and methods may provide for technology that identifies a type of a first activation function, identifies a derivative level of the first activation function, and generates a first instruction based on the type of the first activation function and the derivative level of the first activation function. The technology also includes an accelerator having logic coupled to one or more substrates, the logic including a compute engine including a plurality of arithmetic operators, a multiplexer network coupled to the compute engine, and a controller coupled to the multiplexer network, the controller to detect the first instruction, decode the first instruction to identify the first activation function, and drive the multiplexer network to form first connections between two or more of the plurality of arithmetic operators in accordance with the first activation function, wherein the first connections are to cause the compute engine to conduct the first activation function.

公开(公告)号：US20230273733A1

公开(公告)日：2023-08-31

申请号：US18312289

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： Sagar Varma Sayyaparaju ,  Pramod Udupa ,  Dinesh Kushwaha

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673

Abstract: Systems and methods include technology that receives, with a plurality of cores implemented in one or more of configurable logic or fixed-functionality logic, data associated with a workload, and executing, with the plurality of cores, the workload to process the data and generate partial data. The technology stores the partial data into a memory storage that is accessible by the plurality of cores as the workload is being executed.