公开(公告)号：US20210118510A1

公开(公告)日：2021-04-22

申请号：US17112401

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Joseph F. DOLLER ,  Kristopher H. GAEWSKY ,  Noah MEBANE

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/12

Abstract: Proactively adjusting read voltages at the system level, before performing a read operation on data located in a partially-programmed block in a block-addressable non-volatile memory, can significantly reduce the re-read trigger rate. This reduces the rate of entering a read recovery flow and subsequent read latency. Determining in advance a wordline-specific pattern of wordline offsets associated with past unsuccessful reads in partially-programmed blocks allows read voltages to be proactively adjusted for vulnerable wordlines. Read voltages are restored for subsequent read operations.

公开(公告)号：US20190034330A1

公开(公告)日：2019-01-31

申请号：US15829764

申请日：2017-12-01

Applicant: Intel Corporation

Inventor： Shankar NATARAJAN ,  Aliasgar S. MADRASWALA ,  Kristopher H. GAEWSKY ,  Jason CULP

IPC: G06F12/02 ,  G11C16/34 ,  G11C16/16 ,  G11C16/30

Abstract: An apparatus is described. The apparatus includes a mass storage device having a plurality of storage cells capable of storing more than one bit per cell. The plurality of storage cells are partitionable into a static single level (SLC) buffer, a dynamic SLC buffer and a primary multi-bit storage region. The mass storage device includes charge pump circuitry to program and erase the storage cells such that: a) those of the cells associated with the SLC buffer are to maintain larger stored charge potentials than those of the cells associated with the dynamic SLC buffer; and, b) those of the cells associated with the dynamic SLC buffer, when in SLC mode, are to receive fewer charge pump cycles during a program and/or erase sequence than those of the cells associated with the primary multi-bit storage region.