公开(公告)号：US20190042444A1

公开(公告)日：2019-02-07

申请号：US15957650

申请日：2018-04-19

Applicant: Intel Corporation

Inventor： Shankar NATARAJAN ,  Romesh TRIVEDI

IPC: G06F12/0871 ,  G06F12/02

Abstract: A solid state drive (SSD) includes different segments of nonvolatile (NV) storage media with different access times. The NV media segment with faster access time operates as a cache for the segment with the slower access time. The SSD implements idle eviction from the cache segment to the other segment based on an idle condition of the SSD. The SSD can dynamically change application of the idle eviction based on a power management state indicated for the hardware platform. Thus, a change in power management state of the hardware platform associated with the SSD can cause the SSD to implement idle eviction differently.

公开(公告)号：US20190102102A1

公开(公告)日：2019-04-04

申请号：US15721483

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Shankar NATARAJAN ,  Aliasgar S. MADRASWALA

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0613 ,  G06F3/0649 ,  G06F3/0679 ,  G06F3/068 ,  G06F11/1072 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5622 ,  G11C2211/5641

Abstract: A determination is made that data has to be moved internally within a non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media. A first subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. Concurrently with the copying of the first subset of the plurality of pages, a second subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. In response to completion of the copying of the first subset and the second subset of the plurality of pages, it is determined that the copying of the data from the first type of storage media to the second type of storage media has completed.

公开(公告)号：US20190042140A1

公开(公告)日：2019-02-07

申请号：US15953367

申请日：2018-04-13

Applicant: Intel Corporation

Inventor： Shankar NATARAJAN ,  Romesh TRIVEDI ,  Suresh NAGARAJAN ,  Sriram NATARAJAN

IPC: G06F3/06

Abstract: An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer memory is to store less bits per cell than the non volatile primary storage memory. The solid state drive includes a controller to flush the buffer in response to a buffer flush command received from a host. The controller is to cause the solid state drive to service read/write requests that are newly received from the host in between flushes of smaller portions of the buffer's content that are performed to service the buffer flush command.

公开(公告)号：US20190034105A1

公开(公告)日：2019-01-31

申请号：US15857530

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Shankar NATARAJAN ,  Ramkarthik GANESAN

IPC: G06F3/06 ,  G11C11/56

Abstract: A method is described. The method includes programming multi-bit storage cells of multiple FLASH memory chips in a lower density storage mode. The method also includes programming the multi-bit storage cells of the multiple FLASH memory chips in a higher density storage mode after at least 25% of the storage capacity of the multiple FLASH memory chips has been programmed.

公开(公告)号：US20210097004A1

公开(公告)日：2021-04-01

申请号：US17122152

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Suresh NAGARAJAN ,  Scott CRIPPIN ,  Sahar KHALILI ,  Shankar NATARAJAN ,  Romesh TRIVEDI

IPC: G06F12/1009

Abstract: A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.

公开(公告)号：US20190034330A1

公开(公告)日：2019-01-31

申请号：US15829764

申请日：2017-12-01

Applicant: Intel Corporation

Inventor： Shankar NATARAJAN ,  Aliasgar S. MADRASWALA ,  Kristopher H. GAEWSKY ,  Jason CULP

IPC: G06F12/02 ,  G11C16/34 ,  G11C16/16 ,  G11C16/30

Abstract: An apparatus is described. The apparatus includes a mass storage device having a plurality of storage cells capable of storing more than one bit per cell. The plurality of storage cells are partitionable into a static single level (SLC) buffer, a dynamic SLC buffer and a primary multi-bit storage region. The mass storage device includes charge pump circuitry to program and erase the storage cells such that: a) those of the cells associated with the SLC buffer are to maintain larger stored charge potentials than those of the cells associated with the dynamic SLC buffer; and, b) those of the cells associated with the dynamic SLC buffer, when in SLC mode, are to receive fewer charge pump cycles during a program and/or erase sequence than those of the cells associated with the primary multi-bit storage region.

公开(公告)号：US20210096634A1

公开(公告)日：2021-04-01

申请号：US16586957

申请日：2019-09-28

Applicant: Intel Corporation

Inventor： Richard FASTOW ,  Shankar NATARAJAN ,  Chang Wan HA ,  Chee LAW ,  Khaled HASNAT ,  Chuan LIN ,  Shafqat AHMED

IPC: G06F1/3234 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

公开(公告)号：US20190102296A1

公开(公告)日：2019-04-04

申请号：US15721237

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Shankar NATARAJAN ,  Aliasgar S. MADRASWALA ,  Wayne D. TRAN

IPC: G06F12/0804 ,  G06F3/06

Abstract: In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.

公开(公告)号：US20230395166A1

公开(公告)日：2023-12-07

申请号：US18235727

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Arun Sitaram ATHREYA ,  Shankar NATARAJAN ,  Sriram NATARAJAN ,  Yihua ZHANG ,  Suresh NAGARAJAN

IPC: G11C16/34 ,  G06F3/06 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0688 ,  G11C16/26 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C11/5642

Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

公开(公告)号：US20210151098A1

公开(公告)日：2021-05-20

申请号：US17133459

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shankar NATARAJAN ,  Suresh NAGARAJAN ,  Aliasgar S. MADRASWALA ,  Yihua ZHANG

IPC: G11C11/56 ,  G11C7/10 ,  G11C29/42

Abstract: Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.