公开(公告)号：US20210398906A1

公开(公告)日：2021-12-23

申请号：US16910023

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Gerald PASDAST ,  Juan ZENG ,  Peipei WANG ,  Ahmad SIDDIQUI ,  Lakshmipriya SESHAN

IPC: H01L23/538 ,  H01L23/00

Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.