公开(公告)号：US20180285364A1

公开(公告)日：2018-10-04

申请号：US15475238

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： MAHESH MAMIDIPAKA ,  SRIVATSAVA JANDHYALA ,  ANISH N K ,  NAGADASTAGIRI REDDY C ,  SREENIVAS SUBRAMONEY

IPC: G06F17/30

CPC classification number: G06F16/24578 ,  G06F16/24568 ,  G06F16/248 ,  G06F16/9535

Abstract: A processor may include a plurality of processing elements and a hardware accelerator for selecting data elements. The hardware accelerator may: access an input data set comprising a set of data elements, each data element having a score value; increment bin counters based on the score values of the set of data elements, each bin counter to count a number of data elements with an associated score value; determine a cumulative sum of count values for a sequence of bin counters, the sequence beginning with a first bin counter of the plurality of bin counters; identify a second bin counter in the sequence of bin counters at which the cumulative sum reaches a selection quantity N; and generate an output data set based on a comparison of the set of data elements to a threshold score associated with the second bin counter.