公开(公告)号：US20160197720A1

公开(公告)日：2016-07-07

申请号：US14872556

申请日：2015-10-01

Applicant: Intel Corporation

Inventor： SHAY GUERON ,  WAJDI K FEGHALI ,  VINODH GOPAL ,  RAGHUNANDAN MAKARAM ,  MARTIN G DIXON ,  SRINIVAS CHENNUPATY ,  MICHAEL KOUNAVIS

IPC: H04L9/06 ,  G06F9/38 ,  G06F9/30

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.