公开(公告)号：US20200210472A1

公开(公告)日：2020-07-02

申请号：US16696854

申请日：2019-11-26

Applicant: Intel Corporation

Inventor： BARNAN DAS ,  MAYURESH M. VARERKAR ,  NARAYAN BISWAL ,  STANLEY J. BARAN ,  GOKCEN CILINGIR ,  NILESH V. SHAH ,  ARCHIE SHARMA ,  SHERINE ABDELHAK ,  PRANEETHA KOTHA ,  NEELAY PANDIT ,  JOHN C. WEAST ,  MIKE B. MACPHERSON ,  DUKHWAN KIM ,  LINDA L. HURD ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY

IPC: G06F16/583 ,  G06F16/783 ,  G06K9/00 ,  G06K9/62

Abstract: A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.

公开(公告)号：US20190324746A1

公开(公告)日：2019-10-24

申请号：US15957728

申请日：2018-04-19

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  GUEI-YUAN LUEH ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  CHANDRA S. GURRAM ,  JORGE E. PARRA ,  JUNJIE GU ,  KONRAD TRIFUNOVIC ,  HONG BIN LIAO ,  MIKE B. MACPHERSON ,  SHUBH B. SHAH ,  SHUBRA MARWAHA ,  STEPHEN JUNKINS ,  TIMOTHY R. BAUER ,  VARGHESE GEORGE ,  WEIYU CHEN

IPC: G06F9/30 ,  G06F9/38 ,  G06T1/20

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes a systolic dot product unit to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

公开(公告)号：US20230297373A1

公开(公告)日：2023-09-21

申请号：US18307088

申请日：2023-04-26

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  GUEI-YUAN LUEH ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  CHANDRA S. GURRAM ,  JORGE E. PARRA ,  JUNJIE GU ,  KONRAD TRIFUNOVIC ,  HONG BIN LIAO ,  MIKE B. MACPHERSON ,  SHUBH B. SHAH ,  SHUBRA MARWAHA ,  STEPHEN JUNKINS ,  TIMOTHY R. BAUER ,  VARGHESE GEORGE ,  WEIYU CHEN

IPC: G06F9/30 ,  G06T1/20 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30145 ,  G06T1/20 ,  G06F9/3887 ,  G06F9/3802

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch a single instruction for execution, a decode unit to decode the single instruction into a decoded instruction, wherein the decoded instruction is to cause the graphics processing unit to perform a set of parallel dot product operations on elements of input matrices, and a systolic dot product unit to execute the decoded instruction across one or more parallel processor lanes using multiple systolic layers associated with multiple pipeline stages. The multiple pipeline stages include one or more sets of interconnected multipliers and adders to compute multiple concurrent dot products.

公开(公告)号：US20230177817A1

公开(公告)日：2023-06-08

申请号：US17966067

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： BARNAN DAS ,  MAYURESH M. VARERKAR ,  NARAYAN BISWAL ,  STANLEY J. BARAN ,  GOKCEN CILINGIR ,  NILESH V. SHAH ,  ARCHIE SHARMA ,  SHERINE ABDELHAK ,  PRANEETHA KOTHA ,  NEELAY PANDIT ,  JOHN C. WEAST ,  MIKE B. MACPHERSON ,  DUKHWAN KIM ,  LINDA L. HURD ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY

IPC: G06V10/82 ,  G06F16/783 ,  G06F16/583 ,  G06V10/94 ,  G06V40/10 ,  G06V40/20 ,  G06F18/2413 ,  G06V10/764

CPC classification number: G06V10/82 ,  G06F16/784 ,  G06F16/5838 ,  G06V10/955 ,  G06V40/10 ,  G06V40/23 ,  G06V40/103 ,  G06F18/24143 ,  G06V10/764

Abstract: A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.

公开(公告)号：US20210303299A1

公开(公告)日：2021-09-30

申请号：US17304153

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  GUEI-YUAN LUEH ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  CHANDRA S. GURRAM ,  JORGE E. PARRA ,  JUNJIE GU ,  KONRAD TRIFUNOVIC ,  HONG BIN LIAO ,  MIKE B. MACPHERSON ,  SHUBH B. SHAH ,  SHUBRA MARWAHA ,  STEPHEN JUNKINS ,  TIMOTHY R. BAUER ,  VARGHESE GEORGE ,  WEIYU CHEN

IPC: G06F9/30 ,  G06T1/20 ,  G06F9/38

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes systolic dot product circuitry to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.