公开(公告)号：US20210263993A1

公开(公告)日：2021-08-26

申请号：US17256195

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Maciej URBANSKI ,  Brian J. HICKMANN ,  Michael ROTZIN ,  Krishnakumar NAIR ,  Andrew YANG ,  Brian S. MORRIS ,  Dennis BRADFORD

IPC: G06F17/16 ,  G06F7/523

Abstract: Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described. In one embodiment, a combined fixed-point and floating-point vector multiplication circuit includes at least one switch to change the circuit between a first mode and a second mode, where in the first mode, each multiplier of a set of multipliers is to multiply mantissas from a same element position of a first floating-point vector and a second floating-point vector to produce a corresponding product, shift the corresponding products with a set of shift registers based on a maximum exponent of exponents for the corresponding products determined by a maximum exponent determiner to produce shifted products, perform an numeric conversion operation on the shifted products with a set of numeric conversion circuits based on sign bits from the same element position of the first floating-point vector and the second floating-point vector to produce signed representations of the shifted products, add the signed representations of the shifted products with a set of adders to produce a single product, and normalize the single product with a normalization circuit based on the maximum exponent into a single floating-point resultant, and in the second mode, each multiplier of the set of multipliers is to multiply values from a same element position of a first integer vector and a second integer vector to produce a corresponding product, and add each corresponding product with the set of adders to produce a single integer resultant.

公开(公告)号：US20190205131A1

公开(公告)日：2019-07-04

申请号：US15858278

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Maciej URBANSKI ,  Elmoustapha OULD-AHMED-VALL

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/3001 ,  G06F9/30036

Abstract: Systems, methods, and apparatuses for broadcasting a selected data element and performing an operation in response to a single instruction are described. For example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, at least two packed data source operand identifiers, a packed data destination operand identifier, and an immediate, and execution circuitry to execute the decoded instruction to: broadcast a packed data element from the identified first packed data source operand, wherein the packed data element position to be broadcast is selected based on a value of the immediate, perform operations according to the opcode on the broadcasted packed data element from the identified first packed data source operand and packed data elements of the identified second packed data source operand is described.