公开(公告)号：US20240330048A1

公开(公告)日：2024-10-03

申请号：US18128977

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Efraim ROTEM ,  Stephen H. GUNTHER ,  Rajshree CHABUKSWAR ,  Vishwesh MAGODE RUDRAMUNI ,  Bharath Kumar VEERA ,  Joseph ALBERTS ,  Madhusudan CHIDAMBARAM ,  Zhongsheng WANG ,  Preeti AGARWAL ,  Praveen Kumar GUPTA

IPC: G06F9/48

CPC classification number: G06F9/4893

Abstract: An apparatus and method are described for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores and power management circuitry to associate a plurality of performance values and a plurality of efficiency values with the plurality of cores. In some implementations, each core is associated with at least one performance value and at least one efficiency value. The performance values and efficiency values are used by a scheduler for scheduling threads on the plurality of cores. Some implementations include dynamic core configuration hardware logic coupled to or integral to the power management circuitry to resolve a plurality of configuration requests into a consolidated request for updating one or more performance values of the plurality of performance values and/or one or more efficiency values of the plurality of efficiency values.