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公开(公告)号：US20240330048A1
公开(公告)日：2024-10-03
申请号：US18128977
申请日：2023-03-30
Applicant: Intel Corporation
Inventor： Efraim ROTEM , Stephen H. GUNTHER , Rajshree CHABUKSWAR , Vishwesh MAGODE RUDRAMUNI , Bharath Kumar VEERA , Joseph ALBERTS , Madhusudan CHIDAMBARAM , Zhongsheng WANG , Preeti AGARWAL , Praveen Kumar GUPTA
IPC: G06F9/48
CPC classification number: G06F9/4893
Abstract: An apparatus and method are described for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores and power management circuitry to associate a plurality of performance values and a plurality of efficiency values with the plurality of cores. In some implementations, each core is associated with at least one performance value and at least one efficiency value. The performance values and efficiency values are used by a scheduler for scheduling threads on the plurality of cores. Some implementations include dynamic core configuration hardware logic coupled to or integral to the power management circuitry to resolve a plurality of configuration requests into a consolidated request for updating one or more performance values of the plurality of performance values and/or one or more efficiency values of the plurality of efficiency values.
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公开(公告)号：US20160291680A1
公开(公告)日：2016-10-06
申请号：US15037423
申请日：2013-12-27
Applicant: INTEL CORPORATION
Inventor： Ruoying Mary MA , James G. HERMERDING II , Efraim ROTEM , Jorge P. RODRIGUEZ , Jeffrey A. CARLSON
IPC: G06F1/32
CPC classification number: G06F1/3262 , G06F1/3206 , G06F1/3212 , G06F1/324 , G06F1/3253 , G06F1/3287 , G06F1/3293 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
Abstract: An electronic device comprising: a power monitor to receive system power to be delivered to a processor and to one or more components of a system, the power monitor to provide information corresponding to the system power, and a processor to change a performance of the processor based at least in part on the information corresponding to the system power.
Abstract translation: 一种电子设备，包括：功率监视器，用于接收要传送到处理器的系统功率和系统的一个或多个组件，所述功率监视器提供对应于所述系统功率的信息，以及处理器，用于改变所述处理器的性能 至少部分地基于对应于系统功率的信息。
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3.发明公开公开(公告)号：US20240248862A1
公开(公告)日：2024-07-25
申请号：US18424010
申请日：2024-01-26
Applicant: INTEL CORPORATION
Inventor： Eliezer WEISSMANN , Efraim ROTEM , Doron RAJWAN , Hisham ABU SALAH , Ariel GUR , Guy M. THERIEN , Russell J. FENGER
IPC: G06F13/24 , G06F1/3234 , G06F1/3287 , G06F1/329 , G06F9/30 , G06F9/44 , G06F9/4401
CPC classification number: G06F13/24 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F9/30076 , G06F9/30101 , G06F9/44 , G06F9/4411
Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.
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公开(公告)号：US20220214737A1
公开(公告)日：2022-07-07
申请号：US17705445
申请日：2022-03-28
Applicant: Intel Corporation
Inventor： Hisham ABU SALAH , Efraim ROTEM , Eliezer WEISSMANN , Yoni AIZIK , Daniel D. LEDERMAN
IPC: G06F1/324 , G06F1/3296 , G06F1/3206
Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.
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5.发明公开公开(公告)号：US20240329711A1
公开(公告)日：2024-10-03
申请号：US18128762
申请日：2023-03-30
Applicant: Intel Corporation
Inventor： Rizwana BEGUM , Vasudev BIBIKAR , Efraim ROTEM
IPC: G06F1/3206
CPC classification number: G06F1/3206 , H02J3/32
Abstract: An apparatus and method for workload, power, and performance-aware dynamic core frequency ramp rate. For example, one embodiment of a processor comprises: A processor comprising: a plurality of cores, a first core of the plurality of cores to execute an application comprising one or more workloads; and dynamic ramp rate selection circuitry to determine a core frequency ramp rate to be used to increase a frequency of the first core based, at least in part, on a workload type of a first workload of the one or more workloads.
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Patent Agency Ranking
公开(公告)号：US20240231470A9
公开(公告)日：2024-07-11
申请号：US18491689
申请日：2023-10-20
Applicant: Intel Corporation
Inventor： Efraim ROTEM , Eliezer WEISSMANN , Doron RAJWAN , Yoni AIZIK , Esfir NATANZON , Nir ROSENZWEIG , Nadav SHULMAN , Bart PLACKLE
CPC classification number: G06F1/329 , G06F9/4893
Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.
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7.发明公开公开(公告)号：US20230273795A1
公开(公告)日：2023-08-31
申请号：US18311810
申请日：2023-05-03
Applicant: Intel Corporation
Inventor： Eliezer WEISSMANN , Mark CHARNEY , Michael MISHAELI , Robert VALENTINE , Itai RAVID , Jason W. BRANDT , Gilbert NEIGER , Baruch CHAIKIN , Efraim ROTEM
CPC classification number: G06F9/3851 , G06F9/30076 , G06F9/30101 , G06F9/3836
Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.
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8.发明公开公开(公告)号：US20240329722A1
公开(公告)日：2024-10-03
申请号：US18128946
申请日：2023-03-30
Applicant: Intel Corporation
Inventor： Somvir DAHIYA , Scot KELLAR , Stephen H. GUNTHER , Mark GALLINA , Efraim ROTEM , Prasanna JOTHI
IPC: G06F1/3296 , G06F9/48 , G06F9/50
CPC classification number: G06F1/3296 , G06F9/4893 , G06F9/5094
Abstract: An apparatus and method to control temperature ramp rates including temperature spike detection and control. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions; a power management unit to control power consumption of each core of the plurality of cores, the power management unit comprising: a frequency ramp governor or power step governor to determine a frequency ramp rate limit or power step limit for a core of the plurality of cores based, at least in part, on a present frequency or present power metrics of the core; a frequency limiter or voltage limiter to determine a maximum frequency or maximum voltage of the core based, at least in part, on a measured temperature; and limit resolution circuitry to determine a first frequency or a first power level of the core in accordance with the frequency ramp rate limit or the power step limit and the maximum frequency or maximum voltage.
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9.发明公开公开(公告)号：US20240248722A1
公开(公告)日：2024-07-25
申请号：US18626629
申请日：2024-04-04
Applicant: Intel Corporation
Inventor： Eliezer WEISSMANN , Mark CHARNEY , Michael MISHAELI , Robert VALENTINE , Itai RAVID , Jason W. BRANDT , Gilbert NEIGER , Baruch CHAIKIN , Efraim ROTEM
CPC classification number: G06F9/3851 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/3836 , G06F9/3842
Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.
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公开(公告)号：US20240134443A1
公开(公告)日：2024-04-25
申请号：US18491689
申请日：2023-10-19
Applicant: Intel Corporation
Inventor： Efraim ROTEM , Eliezer WEISSMANN , Doron RAJWAN , Yoni AIZIK , Esfir NATANZON , Nir ROSENZWEIG , Nadav SHULMAN , Bart PLACKLE
CPC classification number: G06F1/329 , G06F9/4893
Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.
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