公开(公告)号：US20200257517A1

公开(公告)日：2020-08-13

申请号：US16857103

申请日：2020-04-23

Applicant: Intel Corporation

Inventor： Larry R. SEATER ,  Benjamin CHEONG ,  Manishkumar T. RANA ,  Stephen A. FIFE ,  James R. HEARN ,  Kevin LIEDTKE

IPC: G06F8/65 ,  G06F1/28

Abstract: Examples described herein relate to a circuit board that includes a device, firmware memory, and a power controller. In some examples, the firmware memory is to store a firmware update and in response to a software-initiated command, the power controller is to reduce power to the device to cause a firmware update of the device and restore power to the device to cause execution of the firmware update. In some examples, the power controller is to reduce power solely to the device independent from power supply to at least one other device. In some examples, device configuration is saved prior to reduction of power to the device and restored to the device after power is restored to the device.

公开(公告)号：US20200266967A1

公开(公告)日：2020-08-20

申请号：US16783077

申请日：2020-02-05

Applicant: Intel Corporation

Inventor： April E. FISHER ,  Benjamin CHEONG ,  Kevin BROSS ,  Manishkumar T. RANA ,  Andrew M. MONK

IPC: H04L7/00

Abstract: Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.