公开(公告)号：US20210019069A1

公开(公告)日：2021-01-21

申请号：US17031721

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Sujoy SEN ,  Thomas E. WILLIS ,  Durgesh SRIVASTAVA ,  Marcelo CINTRA ,  Bassam N. COURY ,  Donald L. FAW ,  Francois DUGAST

IPC: G06F3/06 ,  G06F13/16 ,  H05K5/02

Abstract: Examples herein relate to a system capable of coupling to a remote memory pool, the system comprising: a memory controller and an interface to a connection, the interface coupled to the memory controller. In some examples, the interface is to translate a format of a memory access request to a format accepted by the memory controller and the memory controller is to provide the translated memory access request in a format accepted by a media. In some examples, a controller is to measure a number of addressable regions that are least accessed and cause at least one of the least accessed regions to be evicted to a local or remote memory device with relatively higher latency. In some examples, a remote access manager is to: determine if a region of addressable memory associated with a memory address for an access request is stored in the memory; based on the region of addressable memory associated with the memory address being stored in the memory, determine if a sub-region of addressable memory associated with the memory address is available for access from the memory, wherein the sub-region comprises less than an entirety of the region; and based on the sub-region of addressable memory being available for access from the memory, provide a physical address for use to access data from the sub-region in the memory and copy the data to the cache.

公开(公告)号：US20210149812A1

公开(公告)日：2021-05-20

申请号：US17103802

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy SEN ,  Durgesh SRIVASTAVA ,  Thomas E. WILLIS ,  Bassam N. COURY ,  Marcelo CINTRA

IPC: G06F12/0891 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/1081

Abstract: Examples described herein includes an apparatus comprising: a network interface configured to: receive a request to copy data from a local memory to a remote memory; based on a configuration that the network interface is to manage a cache store the data into the cache and record that the data is stored in the cache. In some examples, store the data in the cache comprises store most recently evicted data from the local memory into the cache. In some examples, the network interface is to store data evicted from the local memory that is not stored into the cache into one or more remote memories.

公开(公告)号：US20210105207A1

公开(公告)日：2021-04-08

申请号：US17103781

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy SEN ,  Durgesh SRIVASTAVA ,  Thomas E. WILLIS ,  Bassam N. COURY ,  Marcelo CINTRA

IPC: H04L12/741 ,  G06F13/28

Abstract: Examples described herein include one or more processors; a network interface; and a direct memory access (DMA) engine communicatively coupled to the one or more processors. In some examples, the DMA engine is to receive a DMA data access request and based on an address in the DMA data access request corresponding to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device. In some examples, the DMA data access request includes a source address, a destination address, and a length. In some examples, if the source address corresponds to a local memory device and the destination address corresponds to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device, wherein the at least one packet includes data stored at the source address.

公开(公告)号：US20210075633A1

公开(公告)日：2021-03-11

申请号：US17103674

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy SEN ,  Thomas E. WILLIS ,  Durgesh SRIVASTAVA ,  Marcelo CINTRA ,  Bassam N. COURY

IPC: H04L12/18 ,  H04L12/54 ,  H04L12/931 ,  H04L29/08

Abstract: Examples described herein relate to a network interface. In some examples, the network interface is to access data designated for transmission in at least one packet to multiple memory nodes by inclusion of an multicast identifier of a memory node group and transmit the at least one packet to a destination network device, wherein the multicast identifier of the memory node group in the at least one packet is to cause an intermediate network device to multicast the packet to multiple memory nodes. In some examples, a memory node comprises a memory pool that includes one or more of: volatile memory, non-volatile memory, or persistent memory. In some examples, the intermediate network device comprises a switch configured to determine network addresses of memory nodes associated with the multicast identifier of the memory node group.

公开(公告)号：US20210073151A1

公开(公告)日：2021-03-11

申请号：US17103602

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy SEN ,  Durgesh SRIVASTAVA ,  Thomas E. WILLIS ,  Bassam N. COURY ,  Marcelo CINTRA

IPC: G06F13/28 ,  G06F12/1081

Abstract: Examples described herein and includes at least one processor and a direct memory access (DMA) device. In some examples, the DMA device is to: access a command from a memory region allocated to receive commands for execution by the DMA device, wherein the command is to access content from a local memory device or remote memory node. In some examples, the DMA device is to: determine if the content is stored in a local memory device or a remote memory node based on a configuration that indicates whether a source address refers to a memory address associated with the local memory device or the remote memory node and whether a destination address refers to a memory address associated with the local memory device or the remote memory node. In some examples, the DMA device is to: copy the content from a local memory device or copy the content to the local memory device using a memory interface.