公开(公告)号：US20240020308A1

公开(公告)日：2024-01-18

申请号：US18364664

申请日：2023-08-03

Applicant: Intel Corporation

Inventor： Maria Cecilia Aguerrebere Otegui ,  Ishwar Bhati ,  Mark Hildebrand ,  Mariano Tepper ,  Theodore Willke

IPC: G06F16/245 ,  G06F16/2453 ,  G06F16/2452

CPC classification number: G06F16/24569 ,  G06F16/2453 ,  G06F16/24526

Abstract: Systems, apparatuses and methods may provide for technology that conducts a traversal of a directed graph in response to a query, retrieves the plurality of vectors from a dynamic random access memory (DRAM) in accordance with the traversal of the directed graphs, wherein each vector in the plurality of vectors is compressed, decompresses the plurality of vectors, determines a similarity between the query and the decompressed plurality of vectors, and generates a response to the query based on the similarity between the query and the decompressed plurality of vectors.

公开(公告)号：US20240419674A1

公开(公告)日：2024-12-19

申请号：US18821201

申请日：2024-08-30

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Ishwar Singh Bhati ,  Maria Cecilia Aguerrebere Otegui ,  Mark Hildebrand ,  Theodore Willke

IPC: G06F16/2458 ,  G06F16/22 ,  G06F16/2457

Abstract: Technology as described herein provides for accessing input vectors and a query vector, the input vectors each having a dimensionality, the query vector associated with a query and having a dimensionality, applying a first vector transformation to the input vectors to generate primary vectors, each of the primary vectors having a dimensionality smaller than the dimensionality associated with the input vectors, applying a second vector transformation to the query vector to generate a modified query vector, the modified query vector having a dimensionality smaller than the dimensionality of the query vector, and conducting a similarity search on the primary vectors based on the modified query vector to generate one or more candidates for the query. In embodiments a first component of the first vector transformation is determined based on an algorithm and a second component of the second vector transformation is determined based on the same algorithm.

公开(公告)号：US20240394310A1

公开(公告)日：2024-11-28

申请号：US18797907

申请日：2024-08-08

Applicant: Intel Corporation

Inventor： Maria Cecilia Aguerrebere Otegui ,  Ishwar Singh Bhati ,  Mark Hildebrand ,  Mariano Tepper ,  Theodore Willke

IPC: G06F16/901 ,  G06F16/22

Abstract: Systems, apparatuses and methods may provide for technology that determines a plurality of means based on a plurality of vectors, wherein each mean in the plurality of means corresponds to center of a cluster, assigns each vector in a plurality of vectors to a mean in the plurality of means, and conducts a compression of the plurality of vectors based on the plurality of means. The technology may also build a directed graph based on the compressed plurality of vectors and update the directed graph. Updating the graph may involve determining a plurality of modified means, detecting that a change in one or more modified means in the plurality of modified means exceeds a threshold, conducting an update of the modified mean(s), and bypassing the update for one or more remaining means in the plurality of modified means.

公开(公告)号：US20240427596A1

公开(公告)日：2024-12-26

申请号：US18800758

申请日：2024-08-12

Applicant: Intel Corporation

Inventor： Mark Hildebrand ,  Mariano Tepper ,  Maria Cecilia Aguerrebere Otegui ,  Ishwar Singh Bhati ,  Theodore Willke

IPC: G06F9/30

Abstract: Systems, apparatuses and methods may provide for technology that conducts, in accordance with a first instruction, a load of a block of data into a register, wherein the block of data is to include a plurality of lanes, conducts, in accordance with a second instruction, a first bitwise mask application to each lane in the plurality of lanes, and extracts a set of vector dimensions from the block of data based on the first bitwise mask application.

公开(公告)号：US20220188228A1

公开(公告)日：2022-06-16

申请号：US17559870

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Sanjeev Trika ,  Mark Hildebrand ,  Jawad Khan

IPC: G06F12/0802

Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a two level memory controller mode that uses a dynamic random access memory as a transparent cache for a persistent memory. For example, a memory controller includes logic to map cached data in the dynamic random access memory to an original address of copied data in the persistent memory. The cached data in the dynamic random access memory is tracked as to whether it is dirty data or clean data with respect to the copied data in the persistent memory. Upon eviction of the cached data from the dynamic random access memory, a writeback of the cached data that has been evicted to the persistent memory is bypassed when the cached data is tracked as dirty data.