公开(公告)号：US20240427596A1

公开(公告)日：2024-12-26

申请号：US18800758

申请日：2024-08-12

Applicant: Intel Corporation

Inventor： Mark Hildebrand ,  Mariano Tepper ,  Maria Cecilia Aguerrebere Otegui ,  Ishwar Singh Bhati ,  Theodore Willke

IPC: G06F9/30

Abstract: Systems, apparatuses and methods may provide for technology that conducts, in accordance with a first instruction, a load of a block of data into a register, wherein the block of data is to include a plurality of lanes, conducts, in accordance with a second instruction, a first bitwise mask application to each lane in the plurality of lanes, and extracts a set of vector dimensions from the block of data based on the first bitwise mask application.

公开(公告)号：US20240394310A1

公开(公告)日：2024-11-28

申请号：US18797907

申请日：2024-08-08

Applicant: Intel Corporation

Inventor： Maria Cecilia Aguerrebere Otegui ,  Ishwar Singh Bhati ,  Mark Hildebrand ,  Mariano Tepper ,  Theodore Willke

IPC: G06F16/901 ,  G06F16/22

Abstract: Systems, apparatuses and methods may provide for technology that determines a plurality of means based on a plurality of vectors, wherein each mean in the plurality of means corresponds to center of a cluster, assigns each vector in a plurality of vectors to a mean in the plurality of means, and conducts a compression of the plurality of vectors based on the plurality of means. The technology may also build a directed graph based on the compressed plurality of vectors and update the directed graph. Updating the graph may involve determining a plurality of modified means, detecting that a change in one or more modified means in the plurality of modified means exceeds a threshold, conducting an update of the modified mean(s), and bypassing the update for one or more remaining means in the plurality of modified means.

公开(公告)号：US11829376B2

公开(公告)日：2023-11-28

申请号：US16868069

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Jawad Khan ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Richard Coulson ,  Theodore Willke

IPC: G06F16/2458 ,  G06N20/00 ,  G06F16/248 ,  G06N7/01

CPC classification number: G06F16/2462 ,  G06F16/248 ,  G06N7/01 ,  G06N20/00

Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.

公开(公告)号：US11500887B2

公开(公告)日：2022-11-15

申请号：US17227045

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Sourabh Dongaonkar ,  Jawad B. Khan ,  Chetan Chauhan ,  Dipanjan Sengupta ,  Mariano Tepper ,  Theodore Willke ,  Richard L. Coulson

IPC: G06F16/24 ,  G06F16/2458 ,  G06N7/00 ,  G06F16/21 ,  G06F16/22 ,  G06F16/248

Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.

公开(公告)号：US20240419674A1

公开(公告)日：2024-12-19

申请号：US18821201

申请日：2024-08-30

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Ishwar Singh Bhati ,  Maria Cecilia Aguerrebere Otegui ,  Mark Hildebrand ,  Theodore Willke

IPC: G06F16/2458 ,  G06F16/22 ,  G06F16/2457

Abstract: Technology as described herein provides for accessing input vectors and a query vector, the input vectors each having a dimensionality, the query vector associated with a query and having a dimensionality, applying a first vector transformation to the input vectors to generate primary vectors, each of the primary vectors having a dimensionality smaller than the dimensionality associated with the input vectors, applying a second vector transformation to the query vector to generate a modified query vector, the modified query vector having a dimensionality smaller than the dimensionality of the query vector, and conducting a similarity search on the primary vectors based on the modified query vector to generate one or more candidates for the query. In embodiments a first component of the first vector transformation is determined based on an algorithm and a second component of the second vector transformation is determined based on the same algorithm.

公开(公告)号：US11989553B2

公开(公告)日：2024-05-21

申请号：US16867948

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F16/23 ,  G06F7/58 ,  G06F9/30 ,  G06F16/13 ,  G06F16/22 ,  G06F16/2455 ,  G06F16/9535 ,  G06F16/9538 ,  H01L27/06

CPC classification number: G06F9/3001 ,  G06F7/58 ,  G06F9/30036 ,  G06F16/137 ,  G06F16/2255 ,  H01L27/0688

Abstract: Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.

公开(公告)号：US20230305709A1

公开(公告)日：2023-09-28

申请号：US18040145

申请日：2020-09-15

Applicant: Intel Corporation

Inventor： Dipanjan Sengupta ,  Mariano Tepper ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0673 ,  G06F3/0659

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.

公开(公告)号：US20200326934A1

公开(公告)日：2020-10-15

申请号：US16913756

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Bryn Keller ,  Mihai Capota ,  Vy Vo ,  Nesreen Ahmed ,  Theodore Willke

IPC: G06F8/75 ,  G06N3/04 ,  G06N3/08

Abstract: Systems, apparatuses and methods may provide for technology that generates a dependence graph based on a plurality of intermediate representation (IR) code instructions associated with a compiled program code, generates a set of graph embedding vectors based on the plurality of IR code instructions, and determines, via a neural network, one of an analysis of the compiled program code or an enhancement of the program code based on the dependence graph and the set of graph embedding vectors. The technology may provide a graph attention neural network that includes a recurrent block and at least one task-specific neural network layer, the recurrent block including a graph attention layer and a transition function. The technology may also apply dynamic per-position recurrence-halting to determine a number of recurring steps for each position in the recurrent block based on adaptive computation time.

公开(公告)号：US20240020308A1

公开(公告)日：2024-01-18

申请号：US18364664

申请日：2023-08-03

Applicant: Intel Corporation

Inventor： Maria Cecilia Aguerrebere Otegui ,  Ishwar Bhati ,  Mark Hildebrand ,  Mariano Tepper ,  Theodore Willke

IPC: G06F16/245 ,  G06F16/2453 ,  G06F16/2452

CPC classification number: G06F16/24569 ,  G06F16/2453 ,  G06F16/24526

Abstract: Systems, apparatuses and methods may provide for technology that conducts a traversal of a directed graph in response to a query, retrieves the plurality of vectors from a dynamic random access memory (DRAM) in accordance with the traversal of the directed graphs, wherein each vector in the plurality of vectors is compressed, decompresses the plurality of vectors, determines a similarity between the query and the decompressed plurality of vectors, and generates a response to the query based on the similarity between the query and the decompressed plurality of vectors.

公开(公告)号：US11640295B2

公开(公告)日：2023-05-02

申请号：US16913756

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Bryn Keller ,  Mihai Capota ,  Vy Vo ,  Nesreen Ahmed ,  Theodore Willke

IPC: G06F8/75 ,  G06N3/08 ,  G06N3/04

Abstract: Systems, apparatuses and methods may provide for technology that generates a dependence graph based on a plurality of intermediate representation (IR) code instructions associated with a compiled program code, generates a set of graph embedding vectors based on the plurality of IR code instructions, and determines, via a neural network, one of an analysis of the compiled program code or an enhancement of the program code based on the dependence graph and the set of graph embedding vectors. The technology may provide a graph attention neural network that includes a recurrent block and at least one task-specific neural network layer, the recurrent block including a graph attention layer and a transition function. The technology may also apply dynamic per-position recurrence-halting to determine a number of recurring steps for each position in the recurrent block based on adaptive computation time.