公开(公告)号：US20240072145A1

公开(公告)日：2024-02-29

申请号：US17893466

申请日：2022-08-23

Applicant: Intel Corporation

Inventor： Megan BECK ,  Joseph BRICE ,  Ryan WOOD ,  Krishna T. MARLA ,  Derek CASELLI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0669 ,  H01L29/775 ,  H01L29/7855

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions.