公开(公告)号：US08990662B2

公开(公告)日：2015-03-24

申请号：US13631937

申请日：2012-09-29

Applicant: Intel Corporation

Inventor： Somnath Paul ,  Sriram R. Vangal ,  Michael D. Abbott ,  Eugene M. Kishinevsky

IPC: H03M13/00 ,  G06F11/14

CPC classification number: G06F11/1443 ,  H04L1/20 ,  H04L1/242

Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.

Abstract translation: 弹性沟通技巧。 数据路径存储要通过链接发送到接收节点的数据。 输出级耦合在数据路径和链路之间。 输出级包括双重采样机制，以保留通过链路传送到接收节点的数据副本。 错误检测电路与输出级耦合以检测数据通路或输出级中的瞬态定时误差。 响应于检测到错误，错误检测电路使得​​输出级发送通过链路发送的数据的副本。

公开(公告)号：US10296338B2

公开(公告)日：2019-05-21

申请号：US15373668

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Brent R. Boswell ,  Banu Meenakshi Nagasundaram ,  Michael D. Abbott ,  Srikanth Dakshinamoorthy ,  Jason M. Howard ,  Joshua B. Fryman

IPC: G06F9/30 ,  G06F9/38

Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.