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    NEURAL NETWORK ACCELERATOR PERFORMING OPERATION WITH MIXED-FORMAT WEIGHTS
    3.
    发明申请
    NEURAL NETWORK ACCELERATOR PERFORMING OPERATION WITH MIXED-FORMAT WEIGHTS 有权

    公开(公告)号：US20250060940A1

    公开(公告)日：2025-02-20

    申请号：US18931973

    申请日：2024-10-30

    Applicant: Intel Corporation

    Inventor： Arnab Raha ,  Michael Wu ,  Deepak Abraham Mathaikutty ,  Daksha Sharma ,  Martin Langhammer

    IPC: G06F7/544 ,  G06F5/01

    Abstract: A data processing unit may include a memory, processing elements (PEs), and a control unit. The memory may store weight blocks within a weight tensor of a neural network operation. Each weight block has an input channel (IC) dimension and an output channel (OC) dimension and includes subblocks. A subblock includes one or more weights having a first data precision and one or more other weights having a second data precision. The second data precision is lower than the first data precision. The control unit may distribute different ones of the subblocks to different ones of the PEs. A PE may receive a subblock and perform a first MAC operation on a weight having a first data precision and a second MAC operation on a weight having a second data precision. The first MAC operation may consume more computation cycles or more multipliers than the second MAC operation.

    HYBRID MULTIPY-ACCUMULATION OPERATION WITH COMPRESSED WEIGHTS
    5.
    发明公开
    HYBRID MULTIPY-ACCUMULATION OPERATION WITH COMPRESSED WEIGHTS 审中-公开

    公开(公告)号：US20230229917A1

    公开(公告)日：2023-07-20

    申请号：US18184101

    申请日：2023-03-15

    Applicant: Intel Corporation

    Inventor： Michael Wu ,  Arnab Raha ,  Deepak Abraham Mathaikutty ,  Nihat Tunali ,  Martin Langhammer

    IPC: G06N3/08 ,  G06F7/544

    CPC classification number: G06N3/08 ,  G06F7/5443

    Abstract: A compute block can perform hybrid multiply-accumulate (MAC) operations. The compute block may include a weight compressing module and a processing element (PE) array. The weight compression module may select a first group of one or more weights and a second group of one or more weights from a weight tensor of a DNN (deep neural network) layer. A weight in the first group is quantized to a power of two value. A weight in the second group is quantized to an integer. The integer and the exponent of the power of two value may be stored in a memory in lieu of the original values of the weights. A PE in the PE array includes a shifter configured to shift an activation of the layer by the exponent of the power of two value and a multiplier configured to multiplying the integer with another activation of the layer.

    METHODS AND APPARATUS TO PERFORM LOW OVERHEAD SPARSITY ACCELERATION LOGIC FOR MULTI-PRECISION DATAFLOW IN DEEP NEURAL NETWORK ACCELERATORS
    6.
    发明申请
    METHODS AND APPARATUS TO PERFORM LOW OVERHEAD SPARSITY ACCELERATION LOGIC FOR MULTI-PRECISION DATAFLOW IN DEEP NEURAL NETWORK ACCELERATORS 有权

    公开(公告)号：US20220292366A1

    公开(公告)日：2022-09-15

    申请号：US17709337

    申请日：2022-03-30

    Applicant: Intel Corporation

    Inventor： Arnab Raha ,  Martin Langhammer ,  Debabrata Mohapatra ,  Nihat Tunali ,  Michael Wu

    IPC: G06N3/10 ,  G06N3/04

    Abstract: Methods, apparatus, systems, and articles of manufacture to perform low overhead sparsity acceleration logic for multi-precision dataflow in deep neural network accelerators are disclosed. An example apparatus includes a first buffer to store data corresponding to a first precision; a second buffer to store data corresponding to a second precision; and hardware control circuitry to: process a first multibit bitmap to determine an activation precision of an activation value, the first multibit bitmap including values corresponding to different precisions; process a second multibit bitmap to determine a weight precision of a weight value, the second multibit bitmap including values corresponding to different precisions; and store the activation value and the weight value in the second buffer when at least one of the activation precision or the weight precision corresponds to the second precision.

    RFID antenna re-location and/or RFID location
    7.
    发明授权
    RFID antenna re-location and/or RFID location 有权

    公开(公告)号：US10706242B2

    公开(公告)日：2020-07-07

    申请号：US15199400

    申请日：2016-06-30

    Applicant: INTEL CORPORATION

    Inventor： Michael Wu ,  Addicam V. Sanjay ,  Daniel Gutwein ,  Hoang Tran Van ,  Kalpana Algotar

    IPC: G06K7/10

    Abstract: In various embodiments, an RFID Antenna/Tag Location Configuration device (RLC) may facilitate placement of one or more RFID antennas in a physical space. The RLC may collect RFID data from tags determine which of the RFID antennas need to be relocated. The RLC may determine, based on collected RFID data, whether each antenna is a dominant antenna and/or has a substantial read rate. If an antenna is not dominant and/or does not exhibit a substantial read-rate, the RLC ma indicate that the antenna should be relocated. The RLC may also be configured to filter collected RFID data prior to using the data for determination of antennas. The RLC may also determine, using the RFID antennas, a physical location of RFID tags in the physical space using detected signal strength for RFID tags. Additional embodiments may be described and/or claimed.

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