公开(公告)号：US12040286B2

公开(公告)日：2024-07-16

申请号：US17886380

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Eunyong Chung ,  Moon Young Jang

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/56 ,  H01L21/67 ,  H01L23/31 ,  H01L25/065 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L21/02362 ,  H01L21/565 ,  H01L21/67288 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0655 ,  H05K1/181 ,  H01L2224/02379 ,  H01L2924/3511

Abstract: Fan-out panel level packages (FOPLPs) comprising warpage control structures and techniques of formation are described. An FOPLP may comprise one or more redistribution layers; a semiconductor die on the one or more redistribution layers; one or more warpage control structures adjacently located next to the semiconductor die; and a mold compound encapsulating the semiconductor die and the one or more warpage control structures on the one or more redistribution layers. The FOPLP can be coupled a board (e.g., a printed circuit board, etc.). The warpage control structures can assist with minimizing or eliminating unwanted warpage, which can occur during or after formation of an FOPLP or a packaged system. In this way, the warpage control structures can assist with reducing costs associated with semiconductor packaging and/or manufacturing of an FOPLP or a packaged system.

公开(公告)号：US11450620B2

公开(公告)日：2022-09-20

申请号：US15969564

申请日：2018-05-02

Applicant: Intel Corporation

Inventor： Eunyong Chung ,  Moon Young Jang

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/56 ,  H01L21/02 ,  H01L23/31 ,  H05K1/18 ,  H01L25/065

Abstract: Fan-out panel level packages (FOPLPs) comprising warpage control structures and techniques of formation are described. An FOPLP may comprise one or more redistribution layers; a semiconductor die on the one or more redistribution layers; one or more warpage control structures adjacently located next to the semiconductor die; and a mold compound encapsulating the semiconductor die and the one or more warpage control structures on the one or more redistribution layers. The FOPLP can be coupled a board (e.g., a printed circuit board, etc.). The warpage control structures can assist with minimizing or eliminating unwanted warpage, which can occur during or after formation of an FOPLP or a packaged system. In this way, the warpage control structures can assist with reducing costs associated with semiconductor packaging and/or manufacturing of an FOPLP or a packaged system.