公开(公告)号：US20250110737A1

公开(公告)日：2025-04-03

申请号：US18827415

申请日：2024-09-06

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Mostafa HAGOG ,  Eliyahu TURIEL

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

公开(公告)号：US20190114176A1

公开(公告)日：2019-04-18

申请号：US16149050

申请日：2018-10-01

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Mostafa HAGOG ,  Eliyahu TURIEL

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

公开(公告)号：US20230052630A1

公开(公告)日：2023-02-16

申请号：US17975596

申请日：2022-10-27

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Mostafa HAGOG ,  Eliyahu TURIEL

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

公开(公告)号：US20220004391A1

公开(公告)日：2022-01-06

申请号：US17216618

申请日：2021-03-29

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Mostafa HAGOG ,  Eliyahu TURIEL

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

公开(公告)号：US20190012178A1

公开(公告)日：2019-01-10

申请号：US16059001

申请日：2018-08-08

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Mostafa HAGOG ,  Eliyahu TURIEL

IPC: G06F9/38 ,  G06F15/80 ,  G06F9/30

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.