公开(公告)号：US20250110737A1

公开(公告)日：2025-04-03

申请号：US18827415

申请日：2024-09-06

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Mostafa HAGOG ,  Eliyahu TURIEL

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

公开(公告)号：US20190114176A1

公开(公告)日：2019-04-18

申请号：US16149050

申请日：2018-10-01

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Mostafa HAGOG ,  Eliyahu TURIEL

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

公开(公告)号：US20190042425A1

公开(公告)日：2019-02-07

申请号：US15948569

申请日：2018-04-09

Applicant: Intel Corporation

Inventor： Eran SHIFER

IPC: G06F12/0815 ,  G06F12/084

Abstract: Techniques for managing multi-level memory and coherency using a unified page granular controller can simplify software programming of both file system handling for persistent memory and parallel programming of host and accelerator and enable better software utilization of host processors and accelerators. As part of the management techniques, a line granular controller cooperates with a page granular controller to support both fine grain and coarse grain coherency and maintain overall system inclusion property. In one example, a controller to manage coherency in a system includes a memory data structure and on-die tag cache to store state information to indicate locations of pages in a memory hierarchy and an ownership state for the pages, the ownership state indicating whether the pages are owned by a host processor, owned by an accelerator device, or shared by the host processor and the accelerator device. The controller can also include logic to, in response to a memory access request from the host processor or the accelerator to access a cacheline in a page in a state indicating ownership by a device other than the requesting device, cause the page to transition to a state in which the requesting device owns or shares the page.

公开(公告)号：US20230315642A1

公开(公告)日：2023-10-05

申请号：US18207602

申请日：2023-06-08

Applicant: Intel Corporation

Inventor： Leon POLISHUK ,  Ayan MANDAL ,  Neetu JINDAL ,  Eran SHIFER ,  Keren MELAMED

IPC: G06F12/0877

CPC classification number: G06F12/0877 ,  G06F2212/60

Abstract: Examples described herein relate to a cache fabric that includes a first layer of a group of routers and includes a second layer of a plurality of clusters of cache controllers. A router of the group of routers can be accessible via an interface that is to receive a memory access request from a processor and select from a group of cache controllers based on a cluster identifier and memory address and provide the memory access request to the selected group of cache controllers. The selected group of cache controllers can receive the memory access request and service a memory access request from a cache device or forward the memory access request to a second cache controller associated with the cache device or a second cache device.

公开(公告)号：US20230052630A1

公开(公告)日：2023-02-16

申请号：US17975596

申请日：2022-10-27

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Mostafa HAGOG ,  Eliyahu TURIEL

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

公开(公告)号：US20220004391A1

公开(公告)日：2022-01-06

申请号：US17216618

申请日：2021-03-29

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Mostafa HAGOG ,  Eliyahu TURIEL

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

公开(公告)号：US20200226066A1

公开(公告)日：2020-07-16

申请号：US16833337

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Zeshan A. CHISHTI ,  Sanjay K. KUMAR ,  Zvika GREENFIELD ,  Philip LANTZ ,  Eshel SERLIN ,  Asaf RUBINSTEIN ,  Robert J. ROYER, JR.

IPC: G06F12/0811 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/02 ,  G06F11/30 ,  G06F1/30

Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory having a near memory and a far memory. The memory controller to maintain first and second caches. The first cache to cache pages recently accessed from the far memory. The second cache to cache addresses of pages recently accessed from the far memory. The second cache having a first level and a second level. The first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level. The memory controller comprising logic circuitry to inform system software that: a) a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory; and/or, b) a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.

公开(公告)号：US20190012178A1

公开(公告)日：2019-01-10

申请号：US16059001

申请日：2018-08-08

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Mostafa HAGOG ,  Eliyahu TURIEL

IPC: G06F9/38 ,  G06F15/80 ,  G06F9/30

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.