公开(公告)号：US20240330559A1

公开(公告)日：2024-10-03

申请号：US18194237

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Raghavendra Vasappanavara ,  Srinivasa R Stg ,  Narendra Nimmagadda ,  Fadi Aboud

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to group design stages in design space optimization of semiconductor design for tool agnostic design flows. An example apparatus is to parse a file to identify a first design stage and a second design stage of a design flow, the first design stage and the second design stage corresponding to a class of design stages. Additionally, the example apparatus is to generate, based on a dictionary file, a group of operations to perform the first design stage and the second design stage, the dictionary file associated with the first design stage and the second design stage. The example apparatus is also to generate adjusted parameters for experimenting on the class of design stages, the adjusted parameters based on the group of operations. Additionally, the example apparatus is to generate instructions based on the group of operations and the adjusted parameters.