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公开(公告)号：US10854249B2
公开(公告)日：2020-12-01
申请号：US16914310
申请日：2020-06-27
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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Patent Agency Ranking
公开(公告)号：US20200143853A1
公开(公告)日：2020-05-07
申请号：US16178346
申请日：2018-11-01
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US20210082481A1
公开(公告)日：2021-03-18
申请号：US17107704
申请日：2020-11-30
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US20200327914A1
公开(公告)日：2020-10-15
申请号：US16914310
申请日：2020-06-27
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US11183226B2
公开(公告)日：2021-11-23
申请号：US17107704
申请日：2020-11-30
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US10706900B2
公开(公告)日：2020-07-07
申请号：US16178346
申请日：2018-11-01
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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