公开(公告)号：US20230343384A1

公开(公告)日：2023-10-26

申请号：US17725384

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Yasir Mohsin Husain ,  Everardo Flores, III ,  Neeladri Sain

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/404 ,  H03K19/20

CPC classification number: G11C11/4085 ,  G11C11/4094 ,  G11C11/4045 ,  H03K19/20

Abstract: A memory device comprising a plurality of first global access lines, second global access lines, first local access lines, and second local access lines; and a plurality of memory cells, wherein a memory cell is coupled to one of the first local access lines and one of the second local access lines. The memory device further comprises a plurality of signal lines to communicate local access line select signals to control a plurality of select devices, wherein a select device selectively couples one of the first global access lines to one of the first local access lines; and a NOR gate to accept the plurality of local access line select signals as inputs and generate a plurality of local access line deselect signals to control a plurality of deselect devices, wherein a deselect device selectively couples one of the first local access lines to a deselect voltage.