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    TECHNOLOGIES FOR DYNAMIC BIASING FOR MEMORY CELLS
    1.
    发明公开
    TECHNOLOGIES FOR DYNAMIC BIASING FOR MEMORY CELLS 审中-公开

    公开(公告)号：US20230317154A1

    公开(公告)日：2023-10-05

    申请号：US17706943

    申请日：2022-03-29

    Applicant: Intel Corporation

    Inventor： Yasir Mohsin Husain ,  Xuming Zhao

    IPC: G11C13/00

    CPC classification number: G11C13/0028 ,  G11C13/0038 ,  H01L45/1233 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

    Abstract: Techniques for dynamically biasing memory cells are disclosed. In the illustrative embodiment, a source follower sets a voltage on a wordline of a memory cell. A bias voltage on the gate of the source follower can be temporarily increased in order to charge the wordline more quickly. In some embodiments, for a read operation, after a demarcation voltage has been applied to the memory cell for the memory cell to change its resistance if it is set, the bias voltage on the gate of the source follower is decreased in order to prevent the memory cell from changing its resistance while the current through the memory cell is being read. In some embodiments, a current mirror can be activated in order to bleed off charge from the wordline to lower the voltage more quickly.

    NOR GATE BASED LOCAL ACCESS LINE DESELECT SIGNAL GENERATION
    2.
    发明公开
    NOR GATE BASED LOCAL ACCESS LINE DESELECT SIGNAL GENERATION 审中-公开

    公开(公告)号：US20230343384A1

    公开(公告)日：2023-10-26

    申请号：US17725384

    申请日：2022-04-20

    Applicant: Intel Corporation

    Inventor： Yasir Mohsin Husain ,  Everardo Flores, III ,  Neeladri Sain

    IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/404 ,  H03K19/20

    CPC classification number: G11C11/4085 ,  G11C11/4094 ,  G11C11/4045 ,  H03K19/20

    Abstract: A memory device comprising a plurality of first global access lines, second global access lines, first local access lines, and second local access lines; and a plurality of memory cells, wherein a memory cell is coupled to one of the first local access lines and one of the second local access lines. The memory device further comprises a plurality of signal lines to communicate local access line select signals to control a plurality of select devices, wherein a select device selectively couples one of the first global access lines to one of the first local access lines; and a NOR gate to accept the plurality of local access line select signals as inputs and generate a plurality of local access line deselect signals to control a plurality of deselect devices, wherein a deselect device selectively couples one of the first local access lines to a deselect voltage.

    TECHNOLOGIES FOR DYNAMIC CURRENT MIRROR BIASING FOR MEMORY CELLS
    5.
    发明公开
    TECHNOLOGIES FOR DYNAMIC CURRENT MIRROR BIASING FOR MEMORY CELLS 审中-公开

    公开(公告)号：US20230186985A1

    公开(公告)日：2023-06-15

    申请号：US17550330

    申请日：2021-12-14

    Applicant: Intel Corporation

    Inventor： Yasir Mohsin Husain

    IPC: G11C13/00

    CPC classification number: G11C13/0038 ,  G11C13/0004 ,  G11C2213/71

    Abstract: Techniques for controlling current through memory cells are disclosed. In the illustrative embodiment, control circuitry may receive an instruction to perform an operation on a memory cell. The control circuitry determines properties of an electrical path that includes the memory cell, such as the capacitance and resistance of the electrical path. The control circuitry determines any additional current that should be applied to the memory cell beyond a base current. The control circuitry can adjust a bias current signal to increase the current through the memory cell when performing the operation based on the electrical characteristics of the path through the memory cell.

    TECHNOLOGIES FOR CONTROLLING CURRENT THROUGH MEMORY CELLS
    6.
    发明申请
    TECHNOLOGIES FOR CONTROLLING CURRENT THROUGH MEMORY CELLS 有权

    公开(公告)号：US20220270680A1

    公开(公告)日：2022-08-25

    申请号：US17184462

    申请日：2021-02-24

    Applicant: Intel Corporation

    Inventor： Noble Narku-Tetteh ,  Yasir Mohsin Husain ,  Ripudaman Singh ,  Nicolas L. Irizarry

    IPC: G11C13/00

    Abstract: Techniques for controlling current through memory cells is disclosed. In the illustrative embodiment, a fine-grained current source and a coarse-grained current source can both be activated to perform an operation on a phase-change memory cell. The coarse-grained current source is briefly activated to charge up the capacitance of an electrical path through the memory cell and then turned off. The fine-grained current source applies a current pulse to perform the operation on the memory cell, such as a reset operation. By charging up the electrical path quickly with the coarse-grained current source, the fine-grained current source can quickly perform the operation on the memory cell, reducing the thermal disturbance caused by the operation on nearby memory cells.

    Technologies for controlling current through memory cells
    7.
    发明授权
    Technologies for controlling current through memory cells 有权

    公开(公告)号：US12154623B2

    公开(公告)日：2024-11-26

    申请号：US17184462

    申请日：2021-02-24

    Applicant: Intel Corporation

    Inventor： Noble Narku-Tetteh ,  Yasir Mohsin Husain ,  Ripudaman Singh ,  Nicolas L. Irizarry

    IPC: G11C13/00

    Abstract: Techniques for controlling current through memory cells is disclosed. In the illustrative embodiment, a fine-grained current source and a coarse-grained current source can both be activated to perform an operation on a phase-change memory cell. The coarse-grained current source is briefly activated to charge up the capacitance of an electrical path through the memory cell and then turned off. The fine-grained current source applies a current pulse to perform the operation on the memory cell, such as a reset operation. By charging up the electrical path quickly with the coarse-grained current source, the fine-grained current source can quickly perform the operation on the memory cell, reducing the thermal disturbance caused by the operation on nearby memory cells.

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