公开(公告)号：US11954563B2

公开(公告)日：2024-04-09

申请号：US17546974

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Nicolas Sawaya ,  Anne Matsuura ,  Justin Hogaboam

IPC: G06N10/70 ,  G06N10/20 ,  G06N10/40

CPC classification number: G06N10/70 ,  G06N10/20 ,  G06N10/40

Abstract: Apparatus and method for error reduction in distributed quantum computing via fusing-and-decomposing gates. For example, one embodiment of an apparatus comprises: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.

公开(公告)号：US20230259765A1

公开(公告)日：2023-08-17

申请号：US18056331

申请日：2022-11-17

Applicant: Intel Corporation

Inventor： Nicolas Sawaya ,  Subrata Goswami ,  Christopher Hughes

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: An agent trained using reinforcement learning (RL) can be used to determine a structure for a complex tensor network. The agent makes incremental changes to a tensor network according to a policy model, where parameters of the policy model were trained using RL. The agent may use a cost function to assess the changes, e.g., to determine whether or not to keep a particular modification. In some cases, tensor networks determined using the RL agent can be used to train a model that can more efficiently select a structure for a complex tensor network.

公开(公告)号：US20230186139A1

公开(公告)日：2023-06-15

申请号：US17546974

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Nicolas Sawaya ,  Anne Matsuura ,  Justin Hogaboam

IPC: G06N10/70 ,  G06N10/20 ,  G06N10/40

CPC classification number: G06N10/70 ,  G06N10/20 ,  G06N10/40

Abstract: Apparatus and method for error reduction in distributed quantum computing via fusing-and-decomposing gates. For example, one embodiment of an apparatus comprises: a quantum module comprising a plurality of qubits; unitary generation logic to combine a group of quantum gates to form at least one unitary operation; decomposition logic to decompose the unitary operation into multiple alternative gate sequences comprising either exact gate sequences or approximate gate sequences; and selection logic to evaluate the multiple alternative gate sequences based on a cost function to identify at least one of the gate sequences.