利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

23 条记录 (耗时 0.021 秒)

    INSTRUCTIONS TO CONVERT FROM FP16 TO BF8
    1.
    发明申请
    INSTRUCTIONS TO CONVERT FROM FP16 TO BF8 有权

    公开(公告)号：US20220206743A1

    公开(公告)日：2022-06-30

    申请号：US17134358

    申请日：2020-12-26

    申请人： Intel Corporation

    发明人： Alexander Heinecke ,  Naveen Mellempudi ,  Robert Valentine ,  Mark Charney ,  Christopher Hughes ,  Evangelos Georganas ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

    IPC分类号： G06F5/00

    摘要： Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.

    8-BIT FLOATING POINT SCALE AND/OR REDUCE INSTRUCTIONS
    5.
    发明公开
    8-BIT FLOATING POINT SCALE AND/OR REDUCE INSTRUCTIONS 审中-公开

    公开(公告)号：US20240045682A1

    公开(公告)日：2024-02-08

    申请号：US17958370

    申请日：2022-10-01

    申请人： Intel Corporation

    发明人： Alexander Heinecke ,  Menachem Adelman ,  Evangelos Georganas ,  Amit Gradstein ,  Christopher Hughes ,  Naveen Mellempudi ,  Simon Rubanovich ,  Uri Sherman ,  Zeev Sperber

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30036 ,  G06F9/3001

    摘要： Techniques for scale and reduction of FP8 data elements are described. An exemplary instruction includes fields for an having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a FP8 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of the exponent of the power of 2 value is a floor value of a FP8 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand.

    Read and write masks update instruction for vectorization of recursive computations over interdependent data
    7.
    发明授权
    Read and write masks update instruction for vectorization of recursive computations over interdependent data 有权
    读写掩码更新指令，用于通过相互依赖的数据向量化递归计算

    公开(公告)号：US09400650B2

    公开(公告)日：2016-07-26

    申请号：US13630247

    申请日：2012-09-28

    申请人： Intel Corporation

    发明人： Mikhail Plotnikov ,  Andrey Naraikin ,  Christopher Hughes

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3013

    摘要： A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor includes the first mask register and the second mask register. The processor includes execution circuitry to execute the mask update instruction. In response to the mask update instruction, the execution circuitry is to invert a given number of mask bits in the first mask register, and also to invert the given number of mask bits in the second mask register.

    摘要翻译： 处理器执行掩码更新指令以对第一屏蔽寄存器和第二掩码寄存器执行更新。 处理器内的寄存器文件包括第一掩码寄存器和第二掩码寄存器。 处理器包括执行掩膜更新指令的执行电路。 响应于掩码更新指令，执行电路将反转第一掩码寄存器中给定数量的掩码位，并且还反转第二掩码寄存器中给定数量的掩码位。

    INSTRUCTIONS TO CONVERT FROM FP16 TO FP8
    9.
    发明公开
    INSTRUCTIONS TO CONVERT FROM FP16 TO FP8 审中-公开

    公开(公告)号：US20240045684A1

    公开(公告)日：2024-02-08

    申请号：US17958380

    申请日：2022-10-01

    申请人： Intel Corporation

    发明人： Alexander Heinecke ,  Menachem Adelman ,  Mark Charney ,  Evangelos Georganas ,  Amit Gradstein ,  Christopher Hughes ,  Naveen Mellempudi ,  Simon Rubanovich ,  Uri Sherman ,  Zeev Sperber ,  Robert Valentine

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30036 ,  G06F9/30018

    摘要： Techniques for converting FP16 to BF8 using bias are described. An example embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed FP8 data using bias terms from the identified source/destination operand and store the packed FP8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed FP8 data using bias terms from the identified source/destination operand and store the packed FP8 data into corresponding data element positions of the identified source/destination operand.