公开(公告)号：US20180101624A1

公开(公告)日：2018-04-12

申请号：US15391511

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Shounak Dhar ,  Mahesh A. Iyer ,  Love Singhal ,  Nikolay Rubanov ,  Saurabh Adya

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5072 ,  G06F2217/84

Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an circuit design on the integrated circuit. Implementing the circuit design may include placing functional blocks at optimal locations that increase the maximum operating frequency of the integrated circuit implementing the optimal circuit design. Logic design equipment may perform timing analysis on an initially placed circuit design that includes initially placed functional blocks. The timing analysis may identify one or more critical paths that may be shortened by moving the critical functional blocks within the circuit design to candidate placement locations. A levelized graph representing possible candidate locations and paths between the possible candidate locations may be traversed in a breadth-first search to generate a shortest updated critical path. The critical functional blocks may be moved to candidate locations corresponding to the updated critical path. The process of shortening critical paths may be iteratively performed.

公开(公告)号：US10318686B2

公开(公告)日：2019-06-11

申请号：US15391511

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Shounak Dhar ,  Mahesh A. Iyer ,  Love Singhal ,  Nikolay Rubanov ,  Saurabh Adya

IPC: G06F17/50

Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an circuit design on the integrated circuit. Implementing the circuit design may include placing functional blocks at optimal locations that increase the maximum operating frequency of the integrated circuit implementing the optimal circuit design. Logic design equipment may perform timing analysis on an initially placed circuit design that includes initially placed functional blocks. The timing analysis may identify one or more critical paths that may be shortened by moving the critical functional blocks within the circuit design to candidate placement locations. A levelized graph representing possible candidate locations and paths between the possible candidate locations may be traversed in a breadth-first search to generate a shortest updated critical path. The critical functional blocks may be moved to candidate locations corresponding to the updated critical path. The process of shortening critical paths may be iteratively performed.