公开(公告)号：US09541949B2

公开(公告)日：2017-01-10

申请号：US14492179

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： Tal Kuzi ,  Nadav Shulman ,  Ofer J. Nathan ,  Ori Levy ,  Itai Feit

IPC: G06F1/14 ,  G06F11/16 ,  G06F9/50

CPC classification number: G06F1/14 ,  G06F9/50 ,  G06F11/1658 ,  G06F2201/835

Abstract: In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括用于存储处理器的时间戳计数的主计数器，以及多个核心，每个核心包括用于存储核心时间戳计数的核心计数器。 处理器还包括响应于核心中的去同步事件的同步逻辑：获得主计数器的值; 使用主计数器的值来启动第一核心计数器，其中第一核心计数器包括在第一核心中; 将第一核心计数器的同步数字与指示主计数器的同步数字的值的同步信号进行比较; 并且响应于所述同步数字与所述同步信号不匹配的确定，基于所述同步信号的等待时间值来调整所述第一核心计数器的第一数字子集。 描述和要求保护其他实施例。