公开(公告)号：US10394300B2

公开(公告)日：2019-08-27

申请号：US15966397

申请日：2018-04-30

申请人： Intel Corporation

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/28 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/26

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US20170090945A1

公开(公告)日：2017-03-30

申请号：US14866584

申请日：2015-09-25

申请人： Intel Corporation

发明人： Doron Rajwan ,  Eliezer Weissmann ,  Yoni Aizik ,  Itai Feit ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC分类号： G06F9/44 ,  G06F1/24

CPC分类号： G06F11/3024 ,  G01V11/002 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3452 ,  G06F11/348 ,  G06F2201/88

摘要： Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.

公开(公告)号：US09541949B2

公开(公告)日：2017-01-10

申请号：US14492179

申请日：2014-09-22

申请人： Intel Corporation

发明人： Tal Kuzi ,  Nadav Shulman ,  Ofer J. Nathan ,  Ori Levy ,  Itai Feit

IPC分类号： G06F1/14 ,  G06F11/16 ,  G06F9/50

CPC分类号： G06F1/14 ,  G06F9/50 ,  G06F11/1658 ,  G06F2201/835

摘要： In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括用于存储处理器的时间戳计数的主计数器，以及多个核心，每个核心包括用于存储核心时间戳计数的核心计数器。 处理器还包括响应于核心中的去同步事件的同步逻辑：获得主计数器的值; 使用主计数器的值来启动第一核心计数器，其中第一核心计数器包括在第一核心中; 将第一核心计数器的同步数字与指示主计数器的同步数字的值的同步信号进行比较; 并且响应于所述同步数字与所述同步信号不匹配的确定，基于所述同步信号的等待时间值来调整所述第一核心计数器的第一数字子集。 描述和要求保护其他实施例。

公开(公告)号：US20220113779A1

公开(公告)日：2022-04-14

申请号：US17645202

申请日：2021-12-20

申请人： Intel Corporation

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/28 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/26

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US10474216B2

公开(公告)日：2019-11-12

申请号：US14971302

申请日：2015-12-16

申请人： Intel Corporation

发明人： Doron Rajwan ,  Dorit Shapira ,  Itai Feit ,  Nadav Shulman ,  Efraim (Efi) Rotem ,  Tal Kuzi ,  Eliezer Weissmann ,  Tomer Ziv ,  Nir Rosenzweig

IPC分类号： G06F1/32 ,  G06F13/42 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

摘要： A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.

公开(公告)号：US11175712B2

公开(公告)日：2021-11-16

申请号：US16527150

申请日：2019-07-31

申请人： Intel Corporation

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/28 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/26 ,  G06F1/3296

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US20180314307A1

公开(公告)日：2018-11-01

申请号：US15966397

申请日：2018-04-30

申请人： Intel Corporation

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/28 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/28 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US09864667B2

公开(公告)日：2018-01-09

申请号：US14866584

申请日：2015-09-25

申请人： Intel Corporation

发明人： Doron Rajwan ,  Eliezer Weissmann ,  Yoni Aizik ,  Itai Feit ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC分类号： G06F11/30 ,  G06F11/34 ,  G06F1/32

CPC分类号： G06F11/3024 ,  G01V11/002 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3452 ,  G06F11/348 ,  G06F2201/88

摘要： Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.

公开(公告)号：US09367114B2

公开(公告)日：2016-06-14

申请号：US13793037

申请日：2013-03-11

申请人： Intel Corporation

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/28 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括具有多个核心的核心域和具有第一逻辑的功率控制器，该第一逻辑接收第一请求以将核心域的第一核心的工作电压增加到第二电压，以指示电压 调节器将工作电压增加到临时电压，然后指示电压调节器将工作电压增加到第二电压。 描述和要求保护其他实施例。

公开(公告)号：US20160259389A1

公开(公告)日：2016-09-08

申请号：US15157553

申请日：2016-05-18

申请人： Intel Corporation

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/28 ,  G06F1/32 ,  G06F1/26

CPC分类号： G06F1/28 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括具有多个核心的核心域和具有第一逻辑的功率控制器，该第一逻辑接收第一请求以将核心域的第一核心的工作电压增加到第二电压，以指示电压 调节器将工作电压增加到临时电压，然后指示电压调节器将工作电压增加到第二电压。 描述和要求保护其他实施例。