公开(公告)号：US09396056B2

公开(公告)日：2016-07-19

申请号：US14214910

申请日：2014-03-15

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Robert Valentine ,  Offer Levy ,  Michael Mishaeli ,  Gal Ofir

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0721 ,  G06F11/073

Abstract: In some disclosed embodiments instruction execution logic provides conditional memory fault assist suppression. Some embodiments of processors comprise a decode stage to decode one or more instruction specifying: a set of memory operations, one or more register, and one or more memory address. One or more execution units, responsive to the one or more decoded instruction, generate said one or more memory address for the set of memory operations. Instruction execution logic records one or more fault suppress bits to indicate whether one or more portion of the set of memory operations are masked. Fault generation logic is suppressed from considering a memory fault corresponding to a faulting one of the set of memory operations when said faulting one of the set of memory operations corresponds to a portion of the set of memory operations that is indicated as masked by said one or more fault suppress bits.

Abstract translation: 在一些公开的实施例中，指令执行逻辑提供条件存储器故障辅助抑制。 处理器的一些实施例包括解码级，以对一个或多个指令进行解码，该指令指定：一组存储器操作，一个或多个寄存器和一个或多个存储器地址。 响应于一个或多个解码指令的一个或多个执行单元为该组存储器操作生成所述一个或多个存储器地址。 指令执行逻辑记录一个或多个故障抑制位以指示该组存储器操作中的一个或多个部分被屏蔽。 当所述一组存储器操作中的所述故障之一对应于由所述一组存储器操作屏蔽的所述一组存储器操作的一部分时，故障产生逻辑被抑制为考虑与所述一组存储器操作中的故障的一个存储器操作相对应的存储器故障， 更多的故障抑制位。