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    SYSTEMS, APPARATUSES, AND METHODS FOR AUTONOMOUS FUNCTIONAL TESTING OF A PROCESSOR
    3.
    发明申请
    SYSTEMS, APPARATUSES, AND METHODS FOR AUTONOMOUS FUNCTIONAL TESTING OF A PROCESSOR 有权

    公开(公告)号：US20230102991A1

    公开(公告)日：2023-03-30

    申请号：US17484542

    申请日：2021-09-24

    申请人： Intel Corporation

    发明人： Michael Mishaeli ,  Edward Brazil ,  Bryan J. Gran ,  Ohad Itzhaki

    IPC分类号： G06F11/22 ,  G06F11/273 ,  G06F11/263

    摘要： Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.

    Branch prediction unit in service of short microcode flows
    4.
    发明授权
    Branch prediction unit in service of short microcode flows 有权

    公开(公告)号：US11029953B2

    公开(公告)日：2021-06-08

    申请号：US16453704

    申请日：2019-06-26

    申请人： Intel Corporation

    发明人： Michael Mishaeli ,  Ido Ouziel ,  Jared Warner Stark, IV

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/12

    摘要： Disclosed embodiments relate to the usage of a branch prediction unit in service of performance sensitive microcode flows. In one example, a processor includes a branch prediction unit (BPU) and a pipeline including a fetch stage to fetch an instruction specifying an opcode, an operand, and a loop condition based on the operand, wherein the BPU is to generate a hint reflecting a predicted result of the loop condition, a decode stage to generate either a first or a second micro-operation flow as per the hint, the pipeline to begin executing the generated micro-operation flow; a read stage to read the operand and resolve the loop condition; and execution circuitry to continue the generated micro-operation flow if the prediction was correct, and, otherwise, to flush the pipeline, update the prediction, and switch from the generated micro-operation flow to the other of the first and second micro-operation flows.

    Memory copy instructions, processors, methods, and systems
    5.
    发明授权
    Memory copy instructions, processors, methods, and systems 有权

    公开(公告)号：US10261790B2

    公开(公告)日：2019-04-16

    申请号：US15086686

    申请日：2016-03-31

    申请人： INTEL CORPORATION

    发明人： Michael Mishaeli

    IPC分类号： G06F9/30 ,  G06F9/38

    摘要： A processor includes a decode unit to decode a memory copy instruction that indicates a start of a source memory operand, a start of a destination memory operand, and an initial amount of data to be copied from the source memory operand to the destination memory operand. An execution unit, in response to the memory copy instruction, is to copy a first portion of data from the source memory operand to the destination memory operand before an interruption. A descending copy direction is to be used when the source and destination memory operands overlap. In response to the interruption, when the descending copy direction is used, the execution unit is to store a remaining amount of data to be copied, but is not to indicate a different start of the source memory operand, and is not to indicate a different start of the destination memory operand.

    Compacted context state management
    6.
    发明授权
    Compacted context state management 有权

    公开(公告)号：US09898330B2

    公开(公告)日：2018-02-20

    申请号：US14076341

    申请日：2013-11-11

    申请人： Intel Corporation

    发明人： Atul Khare ,  Leena Puthiyedath ,  Asit Mallick ,  Jim Coke ,  Michael Mishaeli ,  Gilbert Neiger ,  Vivekananthan Sanjeepan ,  Jason Brandt

    IPC分类号： G06F9/46 ,  G06F9/30

    CPC分类号： G06F9/461 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/30101

    摘要： Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

    Instruction and logic for store broadcast and power management
    8.
    发明授权
    Instruction and logic for store broadcast and power management 有权
    商店广播和电源管理的指导和逻辑

    公开(公告)号：US09501132B2

    公开(公告)日：2016-11-22

    申请号：US14453341

    申请日：2014-08-06

    申请人： Intel Corporation

    发明人： Michael Mishaeli ,  Stanislav Shwartsman ,  Gal Ofir ,  Yulia Kurolap

    IPC分类号： G06F1/32 ,  G06F9/30 ,  G06F15/78

    CPC分类号： G06F1/3287 ,  G06F1/32 ,  G06F9/30145 ,  G06F15/7807 ,  Y02D10/171 ,  Y02D50/20

    摘要： A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit. The decode unit includes logic to decode a store broadcast instruction of a specified width. The LPG includes logic to selectively provide power to the locally-gated circuitry, activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations, and deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry. The execution unit includes logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor.

    摘要翻译： 处理器包括具有本地门控电路的核心，解码单元，耦合到本地门控电路的本地电源门（LPG）以及执行单元。 解码单元包括用于解码指定宽度的存储广播指令的逻辑。 LPG包括用于选择性地向本地门控电路提供电力的逻辑，激活本地门控电路的第一部分以执行完全高速缓存行存储器操作的功率，以及去激活局部门控电路的第二部分的功率 本地门控电路。 执行单元包括由用于执行全高速缓存行存储器操作的本地门控电路的第一部分执行存储广播指令，存储广播指令以存储指定宽度的数据以存储处理器的逻辑。

    REDUCING SILENT DATA ERRORS USING A HARDWARE MICRO-LOCKSTEP TECHNIQUE
    10.
    发明公开
    REDUCING SILENT DATA ERRORS USING A HARDWARE MICRO-LOCKSTEP TECHNIQUE 审中-公开

    公开(公告)号：US20230273811A1

    公开(公告)日：2023-08-31

    申请号：US17682091

    申请日：2022-02-28

    申请人： Intel Corporation

    发明人： Michael Mishaeli ,  Eyal Oz-Sinay ,  Gavri Berger ,  Gal Ofir ,  Tomer Weiner ,  Arkady Bramnik

    IPC分类号： G06F9/48 ,  G06F9/22

    CPC分类号： G06F9/4843 ,  G06F9/22

    摘要： In one embodiment, an apparatus includes: an instruction fetch circuit to fetch instructions; a decode circuit coupled to the instruction fetch circuit to decode the fetched instructions into micro-operations (pops); a scheduler coupled to the decode circuit to schedule the pops for execution; and an execution circuit coupled to the scheduler, the execution circuit comprising a plurality of execution ports to execute the pops. The scheduler may be configured to: schedule at least some pops of a first type for redundant execution on symmetric execution ports of the plurality of execution ports; and schedule pops of a second type for non-redundant execution on a single execution port of the plurality of execution ports. Other embodiments are described and claimed.