公开(公告)号：US20190042443A1

公开(公告)日：2019-02-07

申请号：US15910938

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Maciej MACIEJEWSKI ,  Piotr PELPINSKI ,  Grzegorz JERECZEK ,  Jakub RADTKE ,  Wojciech MALIKOWSKI ,  Pawel MAKOWSKI

IPC: G06F12/0871 ,  G06F12/0811

Abstract: Examples may include techniques to manage data in a data acquisition system including allocating memory in a first stage buffer; storing data received by a data provider into the allocated memory in the first stage buffer; and storing a key identifying the stored data and an address in the first stage buffer for the stored data in an entry in a first keys data structure. Further steps include receiving a request from a filtering unit to get the stored data from the first stage buffer, the request including the key; retrieving the address in the first stage buffer from the entry in the first keys data structure associated with the key; and returning the address in the first stage buffer to the filtering unit. Further steps include receiving a request to store at least a portion of the stored data in a second stage buffer, the request including the key; moving the at least a portion of the stored data from the first stage buffer to the second stage buffer; moving the key from the first keys data structure to a second keys data structure; updating an address for the second stage buffer of the at least a portion of the stored data in the second keys data structure; and freeing memory allocated to the stored data in the first stage buffer.