公开(公告)号：US20190042443A1

公开(公告)日：2019-02-07

申请号：US15910938

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Maciej MACIEJEWSKI ,  Piotr PELPINSKI ,  Grzegorz JERECZEK ,  Jakub RADTKE ,  Wojciech MALIKOWSKI ,  Pawel MAKOWSKI

IPC: G06F12/0871 ,  G06F12/0811

Abstract: Examples may include techniques to manage data in a data acquisition system including allocating memory in a first stage buffer; storing data received by a data provider into the allocated memory in the first stage buffer; and storing a key identifying the stored data and an address in the first stage buffer for the stored data in an entry in a first keys data structure. Further steps include receiving a request from a filtering unit to get the stored data from the first stage buffer, the request including the key; retrieving the address in the first stage buffer from the entry in the first keys data structure associated with the key; and returning the address in the first stage buffer to the filtering unit. Further steps include receiving a request to store at least a portion of the stored data in a second stage buffer, the request including the key; moving the at least a portion of the stored data from the first stage buffer to the second stage buffer; moving the key from the first keys data structure to a second keys data structure; updating an address for the second stage buffer of the at least a portion of the stored data in the second keys data structure; and freeing memory allocated to the stored data in the first stage buffer.

公开(公告)号：US20230051806A1

公开(公告)日：2023-02-16

申请号：US17979687

申请日：2022-11-02

Applicant: Intel Corporation

Inventor： Kapil KARKRA ,  Wojciech MALIKOWSKI ,  Mariusz BARCZAK ,  Shirish BAHIRAT

IPC: G06F3/06

Abstract: A host Flash Translation Layer (FTL) synchronizes host FTL operations with the drive FTL operations to reduce write amplification and over-provisioning. Embodiments of FTL synchronization map, at the host FTL software (SW) stack level, logical bands in which data is managed, referred to as host bands, to the physical bands on a drive where data is stored. The host FTL tracks validity levels of data managed in host bands to determine validity levels of data stored in corresponding physical bands, and optimizes defragmentation operations (such as garbage collection processes and trim operations) applied by the host FTL SW stack to the physical bands based on the tracked validity levels.

公开(公告)号：US20230139729A1

公开(公告)日：2023-05-04

申请号：US18089717

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Mariusz BARCZAK ,  Wojciech MALIKOWSKI ,  Mateusz KOZLOWSKI ,  Lukasz LASEK ,  Artur PASZKIEWICZ ,  Krzysztof SMOLINSKI

IPC: G06F12/0802

Abstract: To increase the availability of a non-volatile cache for use by workloads, the non-volatile cache is dynamically assigned to workloads. The non-volatile cache assigned to a workload can be reduced or increased on demand. A cache space manager ensures that the physical non-volatile cache is available to be assigned prior to assigning. A workload analyzer recognizes a sequential or random workload and requests to reduce the cache space assigned for the sequential or random workload. The workload analyzer recognizes a locality workload, waits until cache space is available in the non-volatile cache and requests an increase of cache space for the locality workload.

公开(公告)号：US20190042097A1

公开(公告)日：2019-02-07

申请号：US15984138

申请日：2018-05-18

Applicant: Intel Corporation

Inventor： Jakub RADTKE ,  Wojciech MALIKOWSKI ,  Tobiasz DOMAGALA

IPC: G06F3/06 ,  G06F12/1009

Abstract: Examples may include a non-volatile memory having a memory including a first table of device physical addresses and a second table of physical device addresses; a control register to receive a clone command to clone a second memory region of the memory as a copy of a first memory region of the memory, the first and second memory regions being referenced by different device physical addresses; and address translation logic, upon receipt of the clone command, create a first entry in the first table for each page of the first memory region and create a second entry in the first table for each page of the second memory region, each first table entry for the first memory region and each first table entry for the second memory region pointing to a same entry in the second table.