公开(公告)号：US20220284539A1

公开(公告)日：2022-09-08

申请号：US17578125

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Hema Chand NALLURI ,  Balaji VEMBU ,  Peter DOYLE ,  Michael APODACA

IPC: G06T1/20 ,  G06T15/00

Abstract: Various embodiments enable loop processing in a command processing block of the graphics hardware. Such hardware may include a processor including a command buffer, and a graphics command parser. The graphics command parser to load graphics commands from the command buffer, parse a first graphics command, store a loop count value associated with the first graphics command, parse a second graphics command and store a loop wrap address based on the second graphics command. The graphics command parser may execute a command sequence identified by the second graphics command, parse a third graphics command, the third graphics command identifying an end of the command sequence, set a new loop count value, and iteratively execute the command sequence using the loop wrap address based on the new loop count value.