-
1.
公开(公告)号:US20190041458A1
公开(公告)日:2019-02-07
申请号:US15945169
申请日:2018-04-04
Applicant: Intel Corporation
Inventor: Tarakesava Reddy Koki , Phani Kumar Alaparthi
IPC: G01R31/317 , H03K5/01 , H05K1/02
Abstract: A processor includes a transmitter to transmit, to a receiver, a differential pair of signals including a positive signal transmitted across a positive conductor and a negative signal transmitted across a negative conductor. A first programmable analog delay circuit is coupled to the positive conductor to provide a first delay to the positive signal and a second programmable analog delay circuit is coupled to the negative conductor to provide a second delay to the negative signal. A controller receives data based on a bit error rate (BER) of the differential pair of signals as measured by a bit error checker of the receiver. In response to determining the BER is less than a threshold BER, the controller stores a first delay value to program the first delay and store a second delay value to program the second delay.
-
2.
公开(公告)号:US11163001B2
公开(公告)日:2021-11-02
申请号:US15945169
申请日:2018-04-04
Applicant: Intel Corporation
Inventor: Tarakesava Reddy Koki , Phani Kumar Alaparthi
Abstract: A processor includes a transmitter to transmit, to a receiver, a differential pair of signals including a positive signal transmitted across a positive conductor and a negative signal transmitted across a negative conductor. A first programmable analog delay circuit is coupled to the positive conductor to provide a first delay to the positive signal and a second programmable analog delay circuit is coupled to the negative conductor to provide a second delay to the negative signal. A controller receives data based on a bit error rate (BER) of the differential pair of signals as measured by a bit error checker of the receiver. In response to determining the BER is less than a threshold BER, the controller stores a first delay value to program the first delay and store a second delay value to program the second delay.
-