公开(公告)号：US11544191B2

公开(公告)日：2023-01-03

申请号：US16830457

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Ambili Vengallur ,  Bharat Daga ,  Pradeep K. Janedula ,  Bijoy Pazhanimala ,  Aravind Babu Srinivasan

IPC: G06F12/0811 ,  G06N3/08 ,  G06F7/544

Abstract: Hardware accelerators for accelerated grouped convolution operations. A first buffer of a hardware accelerator may receive a first row of an input feature map (IFM) from a memory. A first group comprising a plurality of tiles may receive a first row of the IFM. A plurality of processing elements of the first group may compute a portion of a first row of an output feature map (OFM) based on the first row of the IFM and a kernel. A second buffer of the accelerator may receive a third row of the IFM from the memory. A second group comprising a plurality of tiles may receive the third row of the IFM. A plurality of processing elements of the second group may compute a portion of a third row of the OFM based on the third row of the IFM and the kernel as part of a grouped convolution operation.