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1.发明申请VECTOR INDEXED MEMORY ACCESS PLUS ARITHMETIC AND/OR LOGICAL OPERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权向量索引记忆访问加算法和/或逻辑操作处理器，方法，系统和指令公开(公告)号：US20150095623A1
公开(公告)日：2015-04-02
申请号：US14040409
申请日：2013-09-27
Applicant: Intel Corporation
Inventor： Igor Ermolaev , Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Gautam B. Doshi , Rama Kishan V. Malladi , Prasenjit Chakraborty
IPC: G06F9/30
CPC classification number: G06F9/30036 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3887 , G06F15/8007 , G06F2212/454
Abstract: A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.
Abstract translation: 一种处理器，包括用于接收向量索引负载加算术和/或逻辑（A / L）操作加存储指令的解码单元。 该指令是指示要具有多个打包存储器索引的源打包存储器索引操作数。 该指令还用于指示要具有多个压缩数据元素的源打包数据操作数。 处理器还包括与解码单元耦合的执行单元。 执行单元响应于该指令，从与多个打包存储器索引相对应的存储器位置加载多个数据元素，对源打包数据操作数的多个压缩数据元素执行A / L操作， 加载多个数据元素，并将多个结果数据元素存储在与多个打包存储器索引相对应的存储单元中。
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2.发明授权Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructions 有权矢量索引存储器访问加上算术和/或逻辑运算处理器，方法，系统和指令公开(公告)号：US09552205B2
公开(公告)日：2017-01-24
申请号：US14040409
申请日：2013-09-27
Applicant: Intel Corporation
Inventor： Igor Ermolaev , Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Gautam B. Doshi , Rama Kishan V. Malladi , Prasenjit Chakraborty
CPC classification number: G06F9/30036 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3887 , G06F15/8007 , G06F2212/454
Abstract: A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.
Abstract translation: 一种处理器，包括用于接收向量索引负载加算术和/或逻辑（A / L）操作加存储指令的解码单元。 该指令是指示要具有多个打包存储器索引的源打包存储器索引操作数。 该指令还用于指示要具有多个压缩数据元素的源打包数据操作数。 处理器还包括与解码单元耦合的执行单元。 执行单元响应于该指令，从与多个打包存储器索引相对应的存储器位置加载多个数据元素，对源打包数据操作数的多个压缩数据元素执行A / L操作， 加载多个数据元素，并将多个结果数据元素存储在与多个打包存储器索引相对应的存储单元中。
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