公开(公告)号：US20240193078A1

公开(公告)日：2024-06-13

申请号：US18078984

申请日：2022-12-11

Applicant: Intel Corporation

Inventor： Vaibhav SHANKAR ,  Amir Ali RADJAI ,  Jaishankar RAJENDRAN ,  Evrim BINBOGA ,  Prashant KODALI

IPC: G06F12/02 ,  G11C29/54

CPC classification number: G06F12/023 ,  G11C29/54 ,  G06F2212/1044

Abstract: Examples include techniques associated with allocating memory capacity of a memory partitioned to include a first region arranged to include in-line or in-band error correction control (IBECC) memory and a second region arranged to include non-IBECC memory. The first and second regions can be re-sized based on usage of either region reaching a threshold.