公开(公告)号：US20180095910A1

公开(公告)日：2018-04-05

申请号：US15283396

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Stanley Steve KULICK ,  Bezan KAPADIA ,  James SHEHADI ,  Amir Ali RADJAI

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/1673 ,  G06F13/4068

Abstract: A clock domain crossing can occur earlier in time by detection of when a data signal will coincide with a TSV (time slot valid) signal but the valid signal associated with the data signal will not coincide with a TSV. In response to such a detection, the domain crossing circuit can send the valid signal early, resulting in a valid signal sent on an earlier TSV and the data signal sent on a TSV. In one embodiment, such a system can cause a data signal to be received in a slower clock domain on a first edge of the slower clock signal after the data is queued in the faster clock domain. The sending of the early valid indication can reduce latency in transferring data between clock domains.

公开(公告)号：US20240193078A1

公开(公告)日：2024-06-13

申请号：US18078984

申请日：2022-12-11

Applicant: Intel Corporation

Inventor： Vaibhav SHANKAR ,  Amir Ali RADJAI ,  Jaishankar RAJENDRAN ,  Evrim BINBOGA ,  Prashant KODALI

IPC: G06F12/02 ,  G11C29/54

CPC classification number: G06F12/023 ,  G11C29/54 ,  G06F2212/1044

Abstract: Examples include techniques associated with allocating memory capacity of a memory partitioned to include a first region arranged to include in-line or in-band error correction control (IBECC) memory and a second region arranged to include non-IBECC memory. The first and second regions can be re-sized based on usage of either region reaching a threshold.

公开(公告)号：US20240354190A1

公开(公告)日：2024-10-24

申请号：US18759122

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Junjing SHI ,  Wei YANG ,  Amir Ali RADJAI ,  Hongjiu LU

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1004

Abstract: Examples include techniques associated with use of a memory tag with in-line or in-band error correction code (IBECC) memory to provide protection for data to be stored in an address space of a memory device. Examples include adding or including the memory tag with a single error correction double error detection (SECDED) code based on the data to provide IBECC for the data when stored to the first address space in the memory device.

公开(公告)号：US20220262428A1

公开(公告)日：2022-08-18

申请号：US17738923

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Jongwon LEE ,  Tomer LEVY ,  Bill NALE ,  Amir Ali RADJAI

IPC: G11C11/406 ,  G11C11/4078 ,  G11C11/4096

Abstract: Methods and apparatus for row hammer (RH) mitigation and recovery. A host comprising a memory controller is configured to interface with one or more DRAM devices, such as DRAM DIMMs. The memory controller includes host-side RH mitigation logic and the DRAM devices include DRAM-side RH mitigation logic that cooperates with the host-side RH mitigation logic to perform RH mitigation and/or recovery operations in response to detection of RH attacks. The memory controller and DRAM device are configured to support an RH polling mode under which the memory controller periodically polls for RH attack detection indicia on the DRAM device that is toggled when the DRAM device detects an RH attack. The memory controller and DRAM device may also be configured to support an RH ALERT_n mode under which the use of an ALERT_n signal and pin is used to provide an alert to the memory controller to initiate RH mitigation and/or recovery.