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Patent Agency Ranking
1.发明公开公开(公告)号：US20240330049A1
公开(公告)日：2024-10-03
申请号：US18190226
申请日：2023-03-27
Applicant: Intel Corporation
Inventor： Stephen H. Gunther , Praveen Kumar Gupta
IPC: G06F9/48
CPC classification number: G06F9/4893
Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to computing systems with heterogenous processing engines. The heterogenous processing engines may have differing capabilities that change dynamically during system operation due, for example, to changing power budgets, frequencies, voltages, and the like of each processing engine. By dynamically exposing and updating the run-time capability of each processing engine based on current operational conditions, the operating system or system software may select the optimal processing engine for a given task, thereby providing more performance, power efficiencies, and better experience to the user.
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2.发明公开公开(公告)号：US20230297424A1
公开(公告)日：2023-09-21
申请号：US18322636
申请日：2023-05-24
Applicant: Intel Corporation
IPC: G06F9/48 , G06F1/10 , G06F1/08 , G06F1/3296
CPC classification number: G06F9/4893 , G06F1/10 , G06F1/08 , G06F1/3296 , G06F1/324
Abstract: In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.
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公开(公告)号：US11698812B2
公开(公告)日：2023-07-11
申请号：US16554940
申请日：2019-08-29
Applicant: Intel Corporation
CPC classification number: G06F9/4893 , G06F1/08 , G06F1/10 , G06F1/3296 , G06F1/324
Abstract: In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.
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公开(公告)号：US20220261623A1
公开(公告)日：2022-08-18
申请号：US17733692
申请日：2022-04-29
Applicant: Intel Corporation
Inventor： Raymond Jit-Hung Sung , Debabrata Mohapatra , Arnab Raha , Deepak Abraham Mathaikutty , Praveen Kumar Gupta
Abstract: An DNN accelerator includes a column of PEs and an external adder assembly for performing depthwise convolution. Each PE includes register files, multipliers, and an internal adder assembly. Each register file can store an operand (input operand, weight operand, etc.) of the depthwise convolution. The operand includes a sequence of elements, each of which corresponds to a different depthwise channel. A multiplier can perform a sequence of multiplications on two operands, e.g., an input operand and a weight operand, and generate a product operand. The internal adder assembly can accumulate product operands and generate an output operand of the PE. The output operand includes output elements, each of which corresponds to a different depthwise channel. The operands may be reused in different rounds of operations by the multipliers. The external adder assembly can accumulate output operands of multiple PEs and generate an output operand of the PE column.
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公开(公告)号：US12182618B2
公开(公告)日：2024-12-31
申请号：US18322636
申请日：2023-05-24
Applicant: Intel Corporation
IPC: G06F9/48 , G06F1/08 , G06F1/10 , G06F1/3296 , G06F1/324
Abstract: In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.
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