公开(公告)号：US20250118933A1

公开(公告)日：2025-04-10

申请号：US18989657

申请日：2024-12-20

Applicant: Intel Corporation

Inventor： Kai XIAO ,  Diego Mauricio CORTES HERNANDEZ ,  Luz Karine SANDOVAL GRANADOS ,  Jingbo LI ,  Raul ALCALA ARREOLA ,  Quresh BOHRA ,  Jose Manuel CANTOR GONZALEZ ,  Fabio RUIZ MOLINA ,  Carlos Guillermo TERRIQUEZ ARIAS ,  Adriana LOPEZ INIGUEZ

IPC: H01R13/6471 ,  H01R12/70 ,  H01R12/71 ,  H01R12/75 ,  H01R13/04

Abstract: Examples include techniques to improve signal integrity performance for a 3-connector design. The techniques include mounting a socket connector to a first side of a hot swap backplane such that pins of the first socket connector mirror pins of a second socket connector mounted to a second side of the hot swap backplane. The mirrored pins associated with routing data signals. The socket connector having a housing configured to receive a first plug connector of a cable assembly that has a second plug connector coupled with a processor baseboard socket connector.

公开(公告)号：US20240237219A1

公开(公告)日：2024-07-11

申请号：US18610141

申请日：2024-03-19

Applicant: Intel Corporation

Inventor： Ifiok UMOH ,  Luz Karine SANDOVAL GRANADOS ,  Alberto CARRILLO VAZQUEZ ,  Quresh BOHRA ,  Diego Mauricio CORTES HERNANDEZ

IPC: H05K1/18 ,  H01R12/57

CPC classification number: H05K1/181 ,  H01R12/57 ,  H05K2201/10189

Abstract: Methods and apparatus for staggered flip pin SMT (surface mount technology) connectors to reduce crosstalk on high-speed channels. Contact feet on the board-side of a connector are flipped to increase the physical separation between contacts carrying transmit (TX) and contacts carrying receive (RX) signals. Meanwhile, for some embodiments the input receptacle side of the connectors are the same as that defined by standards such as SFF-8482, SFF-8630, SFF-8680 standards and the PCI-SIG, SFF-8639 Module Specification. This enables the connectors to work with existing devices employing these standards, such as NVMe drives. In one aspect, the connectors comprise modified versions of U.2 and U.3 connectors where selected board-side contacts (e.g., TX−, TX+, optional GND) and the mating contact pads used for SMT dual mount termination are staggered. In one aspect, the connector solutions are targeted for PCIe 5.0 and later NVMe implementations, noting the principles and techniques disclosed may apply to other high-speed channels.