公开(公告)号：US20240333263A1

公开(公告)日：2024-10-03

申请号：US18191562

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Chinmay Pradeep Joshi ,  Dinesh Somasekhar ,  David Edward Bradley ,  Radhika Kudva

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372

Abstract: Methods and apparatus are disclosed to improve flip-flop toggle efficiency. An example circuit includes an upper flip-flop latch circuit including a first clock input terminal, a first output terminal, and a first data input terminal, a first gating circuit including a first gating transistor, the first gating transistor including a first power input terminal, a first gating output terminal and a gating signal input terminal, the gating signal input terminal coupled to the first input terminal of the first flip-flop latch circuit, a first clock transistor including a clock power input terminal coupled to the first gating output terminal of the first gating transistor, a clock power output terminal, and a clock signal input terminal coupled to the first clock input terminal of the upper flip-flop latch circuit, and a first latch output transistor including a latch power input terminal, a latch power output terminal coupled to the clock power output terminal of the first clock transistor, and a latch input terminal coupled to an output of a second latch output transistor of the upper flip-flop latch circuit.