公开(公告)号：US20230114164A1

公开(公告)日：2023-04-13

申请号：US17551681

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Aravindh Anantaraman ,  Lakshminarayana Pappu ,  Dongsheng Bi ,  Guadalupe J. Garcia ,  Altug Koker ,  Joydeep Ray ,  Rahul Joshi ,  Shrikul Atulkumar Joshi ,  Mahak Gupta

IPC: G06F12/0871 ,  G06F12/0891 ,  G06F13/16 ,  G06F13/28 ,  G06F15/78

Abstract: In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.