公开(公告)号：US20220413213A1

公开(公告)日：2022-12-29

申请号：US17358912

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Harel Frish ,  John Heck ,  Randal Appleton ,  Stefan Meister ,  Haisheng Rong ,  Joshua Keener ,  Michael Favaro ,  Wesley Harrison ,  Hari Mahalingam ,  Sergei Sochava

IPC: G02B6/12 ,  H01S5/026 ,  G02B6/122

Abstract: Silicon photonic integrated circuit (PIC) on a multi-zone semiconductor on insulator (SOI) substrate having at least a first zone and a second zone. Various optical devices of the PIC may be located above certain substrate zones that are most suitable. A first length of a photonic waveguide structure comprises the crystalline silicon and is within the first zone, while a second length of the waveguide structure is within the second zone. Within a first zone, the crystalline silicon layer is spaced apart from an underlying substrate material by a first thickness of dielectric material. Within the second zone, the crystalline silicon layer is spaced apart from the underlying substrate material by a second thickness of the dielectric material.

公开(公告)号：US12197004B2

公开(公告)日：2025-01-14

申请号：US17358912

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Harel Frish ,  John Heck ,  Randal Appleton ,  Stefan Meister ,  Haisheng Rong ,  Joshua Keener ,  Michael Favaro ,  Wesley Harrison ,  Hari Mahalingam ,  Sergei Sochava

IPC: G02B6/12 ,  G02B6/122 ,  H01S5/026

Abstract: Silicon photonic integrated circuit (PIC) on a multi-zone semiconductor on insulator (SOI) substrate having at least a first zone and a second zone. Various optical devices of the PIC may be located above certain substrate zones that are most suitable. A first length of a photonic waveguide structure comprises the crystalline silicon and is within the first zone, while a second length of the waveguide structure is within the second zone. Within a first zone, the crystalline silicon layer is spaced apart from an underlying substrate material by a first thickness of dielectric material. Within the second zone, the crystalline silicon layer is spaced apart from the underlying substrate material by a second thickness of the dielectric material.